Simulation based FAB scheduler: SeePlan&amp;#x00AE;

Ko, Kuk Won; Yoo, Seock K.; Kim, Byung H.; Park, Bum C.; Park, Eui S.

doi:10.1109/wsc.2010.5679175

Cited by 9 publications

(8 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We aim to load the jobs in the last LP-segment of the ILP on the machines having higher index values, which is a typical machine-selection problem. This machine-selection issue is found to be critical in the LCD Fab application where several photolithography machines experiments with a commercial loading simulation package, SeePLAn ® (Ko et al 2010), which is currently being used as a Fab operation management tool. Figure 6 shows a network model representing five stages (i.e.…”

Section: Generation Of Ordered Set Of Machinesmentioning

confidence: 99%

Backward capacity-filtering for electronics Fabs

Seo

Chung

Kim³

et al. 2016

Production Planning & Control

Self Cite

View full text Add to dashboard Cite

In electronics Fabs such as semiconductor Fabs and liquid crystal display (LCD) Fabs, which are capitalintensive, finite-capacity planning is critical to achieving full-capacity production and on-time production. However, existing finite-capacity planning methods do not adequately reflect the actual capacity profiles of an electronics Fab. In this paper, we propose a new Fab-level capacity-filtering procedure to generate finite-capacity plan: a backward capacity-filtering procedure for generating finite-capacity release plan. When developing the Fab-level filtering procedures, we use stage-level capacity-filtering algorithms as a key building block. In this study, we enhance the previous capacity-filtering algorithms proposed by one of the authors in order to facilitate the practical requirements of electronics Fabs. We apply the proposed capacity-filtering method to a modern LCD-TFT Fab in Korea. Performance analyses demonstrate that the proposed method is superior to existing methods. ARTICLE HISTORYFinite-capacity planning; flexible flow line; electronic Fab; lcd and semiconductor Fab

show abstract

Section: Generation Of Ordered Set Of Machinesmentioning

confidence: 99%

Backward capacity-filtering for electronics Fabs

Seo

Chung

Kim³

et al. 2016

Production Planning & Control

Self Cite

View full text Add to dashboard Cite

show abstract

“…Fig. 2 shows how the SEEPLAN® engine generates loading schedule for each tool in the FAB [6]. The loading simulation engine generates loading schedule and lot history on the basis of master data.…”

Section: A Simulation Modelmentioning

confidence: 99%

“…Move can be determined by simulation from the number of production wafers in step k. Move is the total number of operation in step k. Target move using by pegging. Pegging is a process of labeling WIP lots for a target order which is specified by the due date, quantity, and product specifications including customer information [6]. It decides target for each step, gives current WIP position for each demand, and calculates the latest possible start time (LPST) for each lot.…”

Section: Short-term Bottleneck Detection Frameworkmentioning

confidence: 99%

Short-Term Bottleneck Detection for Process Planning in a FAB

Yang¹,

Chung²,

Park³

2014

IJCCE

View full text Add to dashboard Cite

Abstract-This paper presents a detection process for bottlenecks in a wafer FAB (fabrication) using a simulation approach. In a semiconductor manufacturing industry, a Wafer FAB facility includes various equipment and wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow and batch tools. The performance of a complex manufacturing system (i. e. semiconductor wafer FAB) is mainly decided by a bottleneck. In this paper, we define the problem of a bottleneck process and propose a simulation based framework for short-term (3 shift) bottleneck detection. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.

show abstract

“…The key idea of this paper is to applying the combination of pegging and simulation to determine the dispatching rule by considering states dynamically change of a wafer FAB, whenever a tool determines a lot to be processed next. For the execution of the pegging and simulation, we used a commercial software SEEPLAN® developed by the VMS solutions [7] The remainder of this paper is organized as follows. Section II addresses the approach of this paper for the state-dependent dispatching rule, and Section III describes the experimental design and analyzes experimental results.…”

Section: Introductionmentioning

confidence: 99%

Production Rate Based Dynamic Dispatching Rule Selection in a Wafer FAB

Chung¹,

Ham²,

Park³

2014

IJMMM

View full text Add to dashboard Cite

Abstract-This paper proposes a state-dependent dispatching rule to achieve on-time delivery as well as minimum of mean cycle time in a wafer FAB. Dispatching rule should be selected dynamically according to current system state and operation objective, since condition in a wafer fab is dynamically changed. In this paper, we use 'pegging' to identify a current state of a wafer FAB. Pegging is defined as the process of assigning wafer lots to orders, and it is very essential to meet customers' demands in terms of quality, quantity, and due dates in a wafer FAB. As a result, pegging decides target move for each step, it is necessary to select WIP lot to be processed next. The proposed state-dependent dispatching rule consists of two stages. At the first stage, WIP lots are classified into two groups which has priority, and classical dispatching rule is applied to select a WIP lot at the second stage. The target move and actual move are computed by the combination of pegging and simulation. We developed a simulation model by using MIMAC6, and conducted simulation with SEEPLAN®.

show abstract

Simulation based FAB scheduler: SeePlan®

Cited by 9 publications

References 6 publications

Backward capacity-filtering for electronics Fabs

Backward capacity-filtering for electronics Fabs

Short-Term Bottleneck Detection for Process Planning in a FAB

Production Rate Based Dynamic Dispatching Rule Selection in a Wafer FAB

Contact Info

Product

Resources

About