2019
DOI: 10.1007/s11432-018-9503-9
|View full text |Cite
|
Sign up to set email alerts
|

Simulation of a high-performance enhancement-mode HFET with back-to-back graded AlGaN layers

Abstract: A novel three-dimensional hole gas (3DHG) enhancement-mode (E-mode) heterostructure fieldeffect transistor (HFET) is proposed and investigated. It features back-to-back graded AlGaN (BGA) barrier layers consisting of a positive-graded AlGaN layer and a negative-graded AlGaN layer, which form polarization gradient and subsequently induce the three-dimensional electron gas (3DEG) and 3DHG in the positiveand negative-graded AlGaN layers, respectively. The source and drain are located at the same side of the metal… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1

Citation Types

0
3
0

Year Published

2021
2021
2024
2024

Publication Types

Select...
3
2

Relationship

0
5

Authors

Journals

citations
Cited by 5 publications
(3 citation statements)
references
References 29 publications
0
3
0
Order By: Relevance
“…The group reports a significant enhancement in the drain current metrics in comparison to the conventional counterpart. Further studies on the architecture [19] reveal an enhancement in the OFF -state breakdown characteristics of the proposed architecture by 23 times compared to the conventional architecture, considering similar gate -drain spacings and physical gate lengths. Deng et al [20] further proposed an enhancement to the original stack by incorporating a GaN buffer between the positive and negative graded AlGaN layers.…”
Section: Introductionmentioning
confidence: 94%
See 1 more Smart Citation
“…The group reports a significant enhancement in the drain current metrics in comparison to the conventional counterpart. Further studies on the architecture [19] reveal an enhancement in the OFF -state breakdown characteristics of the proposed architecture by 23 times compared to the conventional architecture, considering similar gate -drain spacings and physical gate lengths. Deng et al [20] further proposed an enhancement to the original stack by incorporating a GaN buffer between the positive and negative graded AlGaN layers.…”
Section: Introductionmentioning
confidence: 94%
“…The process recipe for the Virtual Fabrication of DUT through TCAD presented in this section, is an extension of the work reported by Peng et al [19]. Starting with the standard wafer cleansing procedure, the epi layer stack is grown in accordance with the structure depicted in Fig.…”
Section: Process Recipe For the Virtual Fabrication Of Dutmentioning
confidence: 99%
“…Therefore, obtaining a high resistance buffer without introducing other defects or parasitic channels is significant for GaN devices. Through investigation, polarization induced hole doping is applied to p-GaN HEMT buffer layer in this paper [15][16][17][18][19][20]. The positive polarization induced charge generated by the gradient Al component Al x Ga 1−x N buffer compensates the background electrons [10,21].…”
Section: Introductionmentioning
confidence: 99%