Simulation of Deep-Level Trap Distributions in AlGaN/GaN HEMTs and Its Influence on Transient Analysis of Drain Current

Abstract

AlGaN/GaN high electron mobility transistors for high efficiency power switching applications are susceptible to charge trapping by deep-levels in the GaN buffer resulting in current collapse during gate and drain voltage swings. Although drain-current transient based methodologies have been used consistently to extract trap parameters, the factors affecting the non-exponential nature of the transient are still not well understood. No effort at accurately replicating multiple deep-levels in the GaN buffer to simulate transient response of GaN based power devices has been reported previously. In this work, we present numerical simulation results of HEMTs having multiple discrete trap states as well as band-like distribution of traps in the GaN band-gap. GaN based High Electron Mobility Transistors (HEMT)s, which leverage wide-band-gap related properties, are established as ideal candidates for high-power, high-efficiency and high-frequency applications ranging from RF communication to power conversion. 1,2However, the most unremitting technological challenge limiting the wide-spread adoption of GaN process technology is understanding and predicting their reliability and degradation modes therein. Many concur that most of the reliability-limiting mechanisms and issues are related to the presence of defect states in the forbidden band-gap of GaN, and the subsequent performance degradation associated with such defects. [3][4][5][6][7][8] Drain-current transient analysis experiments have helped shed light on the degradation observed in switching performance, often manifesting in AlGaN/GaN HEMTs as gate lag, drain lag and current collapse.9,10 The collapse is attributed to electron trapping comprised of lateral and vertical components. The lateral component due to tunneling of electrons from the gate to surface states at the AlGaN/insulator interface is facilitated by large bias difference between the gate and drain (under off-state and high drain bias).11-13 However, this phenomenon has been observed to be suppressed by improved passivation techniques.13 Under similar bias conditions, a vertical trapping component, which deteriorates dynamic performance, dominates in devices with improves passivation. The mechanism is expected to involve injection of 2DEG electrons deeper into the buffer and consequent trapping for several buffer designs. [8][9][10][11][12][13] If the traps directly underneath the gate dominate, a shift in dynamic threshold is observed. However, if the traps in the drain access region dominate, they end up depleting the 2DEG in this region thereby increasing the dynamic on-resistance.Much of experimental work identifying GaN buffer traps responsible for deterioration of dynamic performance utilize thermal dependence of the relaxation time constants to extract trap activation energy.11,14 Current relaxation time constants are obtained by taking the derivative of such transients and typically indicate the presence of multiple trapping centers. The extracted derivatives assume an asymmetric shape, with ...

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