Simulation of oxide trapping noise in submicron n-channel MOSFETs

Hou, Fan-Chi; Bosman, G.; Law, Mark E.

doi:10.1109/ted.2003.811395

Cited by 35 publications

(7 citation statements)

References 14 publications

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“…This was also confirmed by low-frequency (LF) noise measurements [3], which are a suitable tool for the study of near-interface border traps in the gate stack [4]. In fact, analyzing the frequency exponent γ of the 1/f γ spectra enables to extract some information on the general nature of the border trap density profile in the high-k oxide [4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 62%

Low-Frequency-Noise-Based Oxide Trap Profiling in Replacement High-k/Metal-Gate pMOSFETs

Simoen¹,

Lee²,

Veloso³

et al. 2013

ECS Trans.

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Low-frequency noise is studied in planar high-k-metal/gate (HKMG) last pMOSFETs in order to study the impact of a postHfO 2 deposition SF 6 -plasma or heat treatment on the oxide trap density and profile. It is shown that the gate oxide quality is improved by lowering the active border trap density for both approaches. At the same time, a detailed analysis of the frequency exponent of the flicker noise spectra reveals that in the case of the SF 6 -plasma, the reduction of the active border trap density occurs more efficiently deeper in the high-k layer, while the opposite holds for the annealed devices, i.e., a lower trap density is found closer to the interfacial SiO 2 layer.

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Section: Introductionmentioning

confidence: 62%

Low-Frequency-Noise-Based Oxide Trap Profiling in Replacement High-k/Metal-Gate pMOSFETs

Simoen¹,

Lee²,

Veloso³

et al. 2013

ECS Trans.

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“…2͑b͔͒, the time constant is expressed as = 0 exp͑y / ͒exp͓͑E C − E͒ / kT͔ with the tunnel attenuation distance ͑Ϸ0.1 nm͒ and 0 ϳ 10 −10 s. 13 In this case maximum time constant 1 can be very long. For example, considering that maximum value of E C − E can be half polysilicon band gap ͑0.56 eV͒, and with y =2 nm ͑typical oxide depth for simulated low-frequency noise at f =1 Hz͒, 13 1 ϳ 10 6 s. For carrier T/D at defects in the bulk of the polysilicon active layer = 0 exp͓͑E C − E͒ / kT͔, and the maximum time constant is much shorter ͑ 1 ϳ 0.003 s͒. In this case, bulk trap contribution cannot explain the 1 / f noise spectra of S IDS / I DS 2 measured for 1 HzՅ f Յ 300 Hz ͑0.03 s Յ Յ 1 s͒ on both FSPC and LSPC TFTs biased from weak to strong inversion ͑see Fig.…”

Section: A Carriers Trapping/detrapping Process At Oxide Trapsmentioning

confidence: 99%

Improvement in the determination by 1/f noise measurements of the interface state distribution in polysilicon thin film transistors in relation with the compensation law of Meyer Neldel

Pichon

Boukhenoufa

Cretu

et al. 2009

Journal of Applied Physics

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Erratum: "Effect of excimer laser annealing on the structural and electrical properties of polycrystalline silicon thin-film transistors" [J.Electrical and noise properties of thin-film transistors on very thin excimer laser annealed polycrystalline silicon films Appl.Low-frequency ͑1 / f͒ noise is studied in N-channel furnace solid phase crystallized ͑FSPC͒ and in laser solid phase crystallized ͑LSPC͒ polysilicon thin film transistors ͑TFTs͒ biased from weak to strong inversion. Noise analysis is supported by the theory of charge carrier trapping/detrapping at the interface tunneling into gate oxide traps. The distribution of interface trap states ͑N T ͒ is deduced from the number of carriers trapped into the oxide. Noise measurements for devices biased from weak to moderate inversion allow the determination of the distribution of deep level trap states associated with dangling bond-type defects ͑N Tdb ͒, whereas measurements from moderate to strong inversion give the distribution of shallow level trap states ͑N Tts ͒ associated with strained bond defects. The noise analysis clearly shows that the slope of both exponential distributions equals to the reverse of the Meyer Neldel energy E MN ͑0.035 and 0.055 eV for FSPC and LSPC TFTs, respectively͒. For LSPC devices the resulting distribution of interface states ͑N T = N Tdb + N Tts ͒ is one decade lower and it is attributed to the effects of the laser annealing on the active layer crystal quality.

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“…Both RTN and 1/f noise can be used to study traps in the gate dielectric, revealing their energy level, capture cross section and position with respect to the interface with the channel (1,6,10). Assuming direct elastic tunneling of carriers, one can derive an oxide trap density profile with depth from a 1/f γ -spectrum, whereby an exponent γ=1 indicates a uniform profile, while γ<1 or γ>1 corresponds with a trap density increasing or decreasing towards the interface (6,(11)(12)(13)(14). As a result, the low-frequency noise magnitude or Power Spectral Density (PSD) may be largely affected by the gate dielectric processing details, whereby it has been shown that the noise PSD usually increases when switching from SiO 2 or SiON to high-κ layers (15)(16)(17)(18)(19).…”

Section: Introductionmentioning

confidence: 99%

(Invited) Impact of the Metal Gate on the Oxide Stack Quality Assessed by Low-Frequency Noise

Simoen¹,

O’Sullivan³

et al. 2017

ECS Trans.

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A review is given about the impact of the metal gate (MG) in a High-κ/Metal Gate (HKMG) stack on the quality and defectivity of the dielectric, assessed by low-frequency (LF) noise spectroscopy. In a first part, processing aspects are discussed, like, the thickness of the MG and the implementation of a gate-last approach. In the latter case, it is shown that both the cleaning (or dummy gate removal), the growth of the interfacial SiO 2 layer (chemical versus thermal) and a post-HfO 2 -deposition heat or SF 6 plasma treatment need to be optimized for reducing the gate oxide trap density. In a second part, different MGs are compared from a viewpoint of noise magnitude. It is generally found that alternatives to the standard TiN gate yield better static and noise performance. Results will be presented both for scaled planar and FinFET technologies; the latter fabricated on either bulk or Silicon-on-Insulator (SOI) substrates. Also results on Gate-All-Around NanoWire FETs (GAA NWFETs) fabricated on SOI will be included.

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Simulation of oxide trapping noise in submicron n-channel MOSFETs

Cited by 35 publications

References 14 publications

Low-Frequency-Noise-Based Oxide Trap Profiling in Replacement High-k/Metal-Gate pMOSFETs

Low-Frequency-Noise-Based Oxide Trap Profiling in Replacement High-k/Metal-Gate pMOSFETs

Improvement in the determination by 1/f noise measurements of the interface state distribution in polysilicon thin film transistors in relation with the compensation law of Meyer Neldel

(Invited) Impact of the Metal Gate on the Oxide Stack Quality Assessed by Low-Frequency Noise

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