Simulation Perspectives of Sub-1V Single-Supply Z<sup>2</sup>-FET 1T-DRAM Cells for Low-Power

Navarro, C.; Márquez, Carlos; Vilanova, Santiago; Lozano, C.; Kwon, Sehyun; Kim, Yong‐Tae; Gamiz, F.

doi:10.1109/access.2019.2907151

Cited by 10 publications

(9 citation statements)

References 20 publications

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“…Therefore, the 1T DRAM could hold ‘1’ and ‘0’ without energy consumption. The energy consumption of the proposed 1T DRAM, the conventional DRAM, and the recently reported 1T DRAMs is compared in Table 3 [ 32 , 38 , 39 , 40 ]; the energy consumption of the write and read operations represented the dynamic energy consumption. The proposed 1T DRAM was superior to the conventional DRAM; it exhibited ~2000 times lower energy consumption than the traditional DRAM.…”

Section: Resultsmentioning

confidence: 99%

Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors

2023

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Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challenges because of their one-transistor (1T) memory behaviors with a capacitorless structure. Although FBFETs have been studied as 1T memory devices, the reliability in an array must be evaluated. Cell reliability is closely related to device malfunction. Hence, in this study, we propose a 1T DRAM consisting of an FBFET with a p+–n–p–n+ silicon nanowire and investigate the memory operation and disturbance in a 3 × 3 array structure through mixed-mode simulations. The 1T DRAM exhibits a write speed of 2.5 ns, a sense margin of 90 μA/μm, and a retention time of approximately 1 s. Moreover, the energy consumption is 5.0 × 10−15 J/bit for the write ‘1’ operation and 0 J/bit for the hold operation. Furthermore, the 1T DRAM shows nondestructive read characteristics, reliable 3 × 3 array operation without any write disturbance, and feasibility in a massive array with an access time of a few nanoseconds.

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Section: Resultsmentioning

confidence: 99%

Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors

2023

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“…The use of alternative materials with a narrow bandgap, such as germanium, is an attractive avenue towards reducing the operating voltage and, hence, the power consumption of Z 2 -FET DRAM cells. This has been demonstrated through numerical simulations [43].…”

Section: Dynamic Memory Cell: Operation As Capacitorless Drammentioning

confidence: 88%

A Review of Sharp-Switching Band-Modulation Devices

et al. 2021

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This paper reviews the recently-developed class of band-modulation devices, born from the recent progress in fully-depleted silicon-on-insulator (FD-SOI) and other ultrathin-body technologies, which have enabled the concept of gate-controlled electrostatic doping. In a lateral PIN diode, two additional gates can construct a reconfigurable PNPN structure with unrivalled sharp-switching capability. We describe the implementation, operation, and various applications of these band-modulation devices. Physical and compact models are presented to explain the output and transfer characteristics in both steady-state and transient modes. Not only can band-modulation devices be used for quasi-vertical current switching, but they also show promise for compact capacitorless memories, electrostatic discharge (ESD) protection, sensing, and reconfigurable circuits, while retaining full compatibility with modern silicon processing and standard room-temperature low-voltage operation.

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“…This work 439 fJ Conventional 1T-1C DRAM [36] >10,000 fJ SiGe QW 1T-DRAM [37] 383 fJ Z 2 -FET [38] 1000~4000 fJ…”

Section: Device Energy Consumption (E = V D × I D × Time)mentioning

confidence: 92%

Capacitorless One-Transistor Dynamic Random-Access Memory with Novel Mechanism: Self-Refreshing

Lee,

Park,

Yoon

et al. 2024

Nanomaterials

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In this paper, we propose for the first time a self-refreshing mechanism in a junctionless field-effect transistor (JLFET) based on one-transistor dynamic random-access memory (1T-DRAM) with a silicon-on-insulator (SOI) structure. The self-refreshing mechanism continuously creates holes by appropriately generating impact ionization during the holding process through the application of an appropriate operation bias voltage. This leads to self-refreshing, which prevents the recombination of holes. When using the self-refreshing mechanism for the proposed device, the sensing margins were 15.4 and 12.7 μA/μm at 300 and 358 K, respectively. Moreover, the device achieved an excellent performance retention time of >500 ms, regardless of the temperature of the 1T-DRAM with a single gate. Furthermore, cell disturbance analysis and voltage optimization were performed to evaluate the in-cell reliability of the proposed device. It also showed excellent performance in terms of energy consumption and writing speed.

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Simulation Perspectives of Sub-1V Single-Supply Z²-FET 1T-DRAM Cells for Low-Power

Cited by 10 publications

References 20 publications

Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors

Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors

A Review of Sharp-Switching Band-Modulation Devices

Capacitorless One-Transistor Dynamic Random-Access Memory with Novel Mechanism: Self-Refreshing

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Simulation Perspectives of Sub-1V Single-Supply Z2-FET 1T-DRAM Cells for Low-Power

Cited by 10 publications

References 20 publications

Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors

Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors

A Review of Sharp-Switching Band-Modulation Devices

Capacitorless One-Transistor Dynamic Random-Access Memory with Novel Mechanism: Self-Refreshing

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Product

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Simulation Perspectives of Sub-1V Single-Supply Z²-FET 1T-DRAM Cells for Low-Power