Simulation Study of the Instability Induced by the Variation of Grain Boundary Width and Trap Density in Gate-All-Around Polysilicon Transistor

Lin, Pole-Shang; Chiu, Yu–Jen; Chen, Frederick; Shirota, R.

doi:10.1109/ted.2021.3059185

Cited by 6 publications

(1 citation statement)

References 30 publications

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“…In addition, the 3-D stacked 1T-DRAM is made of polycrystalline silicon (poly-Si), so high-density 3-D memory arrays can be feasible. Based on their superior advantages in terms of the integrated fabrication technology, the poly-Si-based transistors have been widely used in 3-D memory technology in the past 6 – 8 .…”

Section: Introductionmentioning

confidence: 99%

3-D stacked polycrystalline-silicon-MOSFET-based capacitorless DRAM with superior immunity to grain-boundary’s influence

Lee

Park

Min

et al. 2022

Sci Rep

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In this paper, a capacitorless one-transistor dynamic random access memory (1 T-DRAM) based on a polycrystalline silicon (poly-Si) metal-oxide-semiconductor field-effect transistor with the asymmetric dual-gate (ADG) structure is designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was used within the device due to its low fabrication cost and feasibility in high-density three-dimensional (3-D) memory arrays. We studied the transfer characteristics and memory performances of the single-layer ADG 1 T-DRAMs and the 3-D stacked ADG 1 T-DRAMs and analyze the reliability depending on the location and the number of grain-boundaries (GBs). The relative standard deviation (RSD) of the threshold voltages (Vth) is depending on the location and the number of GBs. The RSDs of the single-layer ADG 1 T-DRAM and the 3-D stacked ADG 1 T-DRAM are 1.58% and 0.68%, respectively. The RSDs of retention time representing the memory performances are 54.7% and 41%, respectively. As a result of the 3-D stacked structure, the averaging effect occurs, which greatly aids in improving the reliability of the memory performances as well as the transfer characteristics of 1 T-DRAMs depending on the influence of GBs. The proposed 3-D stacked ADG 1 T-DRAM helps implement a high-reliability single-cell memory device.

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Section: Introductionmentioning

confidence: 99%

3-D stacked polycrystalline-silicon-MOSFET-based capacitorless DRAM with superior immunity to grain-boundary’s influence

Lee

Park

Min

et al. 2022

Sci Rep

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Thin‐Film Transistors for Integrated Circuits: Fundamentals and Recent Progress

Yan,

Wang,

Yan

et al. 2023

Adv Funct Materials

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High‐performance thin‐film transistors (TFTs) integrated circuits (ICs) have become increasingly necessary to meet the emerging demands such as healthcare, edge computing, and the Internet of Things, etc. This article aims to point out the potential development trends and bottlenecks of TFT ICs, enhancing their performance in terms of electronic performance, stability, consistency, CMOS design, and manufacturing capability. Basic device structures and overall metrics of TFT ICs are explored, as well as their superiority compared to silicon‐based ultrathin chips. Hydrogenated amorphous silicon, low‐temperature polycrystalline silicon, and amorphous oxide semiconductors are widely used in displays due to their ability to be deposited on large areas at low processing temperatures and low cost, and are validated in many prototypes for TFT ICs. Their conduction mechanisms, process flows, performance evaluation, and recent advances are comprehensively viewed. In addition, the potential of emerging low‐dimensional materials as next‐generation channel materials is discussed, along with their limitations and progress in this field. Finally, the major challenges in manufacturing high‐performance TFT ICs and future perspectives are summarized.

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Self-consistent statistical model for current transport in polycrystalline semiconductors

Benford,

Amit

2024

Journal of Applied Physics

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Transport in novel materials, specifically those scaled up to wafer sizes, will be dominated by thermionic emission over charged, randomly oriented grain boundaries. However, the challenges presented by random dopant fluctuation in lightly and moderately doped nano-crystalline materials are yet to be addressed. Here, we present a self-consistent model to describe the transport in polycrystalline materials with medium doping levels, where conductivity is governed by thermionic emission over low and wide barriers. We show that random doping fluctuations contribute to a higher material resistivity, which is explained through a non-linear potential drop over the depletion regions on both sides of the boundary. This leads to a decrease in the exponential slope at the onset of conductivity, down to values of ∼exp⁡(−2.4kT)−1, as well as to asymmetry in the current–voltage characteristics. We demonstrate that the model can be scaled up to several grains and their boundaries, by using commercially available circuit simulators, where non-linearity is realized through look-up tables. We find that an increase in resistivity of up to 18% compared to the nominal, uniformly doped material can be explained simply by the introduction of random dopant fluctuations.

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Simulation Study of the Instability Induced by the Variation of Grain Boundary Width and Trap Density in Gate-All-Around Polysilicon Transistor

Cited by 6 publications

References 30 publications

3-D stacked polycrystalline-silicon-MOSFET-based capacitorless DRAM with superior immunity to grain-boundary’s influence

3-D stacked polycrystalline-silicon-MOSFET-based capacitorless DRAM with superior immunity to grain-boundary’s influence

Thin‐Film Transistors for Integrated Circuits: Fundamentals and Recent Progress

Self-consistent statistical model for current transport in polycrystalline semiconductors

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