Simulations of CMOS pixel sensors with a small collection electrode, improved for a faster charge collection and increased radiation tolerance

Abstract

A: CMOS pixel sensors with a small collection electrode combine the advantages of a small sensor capacitance with the advantages of a fully monolithic design. The small sensor capacitance results in a large ratio of signal-to-noise and a low analogue power consumption, while the monolithic design reduces the material budget, cost and production effort. However, the low electric field in the pixel corners of such sensors results in an increased charge collection time, that makes a fully efficient operation after irradiation and a timing resolution in the order of nanoseconds challenging for pixel sizes larger than approximately forty micrometers. This paper presents the development of concepts of CMOS sensors with a small collection electrode to overcome these limitations, using three-dimensional Technology Computer Aided Design simulations. The studied design uses a 0.18 µm process implemented on a high-resistivity epitaxial layer. K: Solid state detectors, Detector modelling and simulations, Charge induction, Radiationhard detectors A X P : 1903.10190

Increased radiation tolerance of CMOS sensors with small collection electrodes through accelerated charge collection

“…The reconstructed track is then extrapolated to the plane of the DUT; after the planes alignment procedure, tracks are required to have χ 2 /Ndof 4 smaller than 10, the unbiased residual distribution between the track intercept point and the cluster position on the DUT reaches a width of 13.5 µm in both x and y coordinates. 3 The choice of using only a subset of the telescope planes in the reconstruction stems from optimisation studies related to the impact of the multiple scattering on the position resolution 4 The number of degree of freedom of a track is 2*N-4 where N is the number of spacial points used in the fit…”

“…The prototype showed severe charge collection inefficiencies near the pixel edges after irradiation despite the process modification [3]. Detailed investigation including TCAD simulations [4] showed the low lateral electric field near the pixel borders significantly increases the collection time for signal charge generated in that area, especially for pixel pitches above 30µm. Following these results a new prototype has been produced to address these issues: Mini-MALTA.…”

Measurement of the relative response of small-electrode CMOS sensors at Diamond Light Source

“…The same effect is seen for the new designs, as shown for the n − gap design in Figure 7, and the response results summarised in Table 4. Simulations suggest that there are two effects caused by a higher applied voltage: a longer drift path and faster drift along the sensor depth [4]. In the pixel center the faster drift causes better charge collection.…”

“…The second design has a gap in the n − layer, which is expected to have a similar effect on the electric field. Both of the designs have been shown to perform well in TCAD simulations [4]. Each of the designs is implemented with a standard front-end and with a modified front-end featuring enlarged transistors to reduce random telegraph signal (RTS) noise.…”

CLICTD: A monolithic HR-CMOS sensor chip for the CLIC silicon tracker

“…Two different pixel layouts were implemented and manufactured through a process split on different wafers. As illustrated in Figure 1, the first pixel layout is with a continuous deep N-type implant, and the second with a segmented deep N-type implant to increase the lateral field and thereby reduce the charge collection time [4]. In addition, reduced charge sharing is expected because of the gap in the N-implant.…”