Simulations on 130 nm technology 6T SRAM cell for Near-Threshold operation

Kutila, Mika; Paasio, A.; Lehtonen, Teijo

doi:10.1109/iscas.2014.6865359

Cited by 9 publications

(3 citation statements)

References 7 publications

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“…A2 has the same size as the pull-down transistor N2; this allows precharged BL to discharge through them with speed, that makes reliable read operation possible. Leakage through the whole memory cell depends significantly on the widths of N1 and N2, and the minimum leakage can be achieved with widths of 300 nm [9]; the widths of N1 and N2 are close to that.…”

Section: Memorymentioning

confidence: 99%

Design solutions for a low-power SoC platform using near-threshold voltages

2014

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In the future the number of small sensor-based devices is going to increase. The Internet-of-Everything (IoE) vision brings smart miniature electronic devices to objects surrounding our everyday lives. These devices are going to monitor our environment or ourselves. They are also going to execute small tasks based on their observations. Operations of this kind can be done with small low-performance devices. In this paper we present building blocks for a low-power system for sensorbased applications. Our work is aiming for reliable operation with supply voltage of 0.5 V instead of the nominal of 1.2 V. We describe low-power solutions used in 130 nm CMOS technology microprocessor, memory and clock generator. Depending on the component, we have managed to achieve reliable operation with voltages of 0.5-0.8 V. Power consumption of components reduce significantly when operating voltage is scaled down to nearthreshold region.

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Section: Memorymentioning

confidence: 99%

Design solutions for a low-power SoC platform using near-threshold voltages

2014

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“…R1 and R2 of 8T SRAM have a width that minimizes the leakage through them. Leak current through NMOS depends on the width of the channel, and the minimum leakage is achieved with 300 nm width [5]. The lengths of all transistors are set to 200 nm, which is larger than the nominal 130 nm; this makes the leakage smaller, and bigger size gives protection against manufacturing inaccuracies and therefore reduces variations in the threshold voltages.…”

Section: Circuitsmentioning

confidence: 99%

Comparison of 130 nm technology 6T and 8T SRAM cell designs for Near-Threshold operation

Kutila

Paasio

Lehtonen

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Power consumption is an important aspect of almost any electrical device design. Near-Threshold Computing (NTC) is a voltage scaling technique that makes it possible to reduce the power consumption of CMOS devices with the cost of speed and reliability. We are using NTC to design low-power cache memory circuit for a low-performance sensor-based system. Caches consume noteworthy portions of power and area of this kind of systems, and therefore reducing their power consumption has a meaningful impact on the overall power consumption of the whole system. In this paper, 8T SRAM and 6T SRAM memory cells are compared in order to establish guidelines for choosing SRAM cell constructions for NTC systems. 8T SRAM is traditionally concerned as a more reliable memory cell, but we have managed to design 6T SRAM which executes read operation with an acceptaple reliability; read being the most vulnerable operation of conventional 6T SRAM cell. Also, our 6T SRAM cell has 31 % smaller area and smaller power consumption.

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“…This, in turn, raises the temperature of the chip and restricts the chip activity. Therefore new power optimization techniques are required to maintain the chip activity and to limit the heat generated [2]. Voltage scaling is one of the best techniques to obtain required power efficiency, but it leads to high leakage current and low speed of operation [3].…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Heterojunction Tunneling Transistor (HETT) based Standard 6T SRAM Cell

Satyanarayana¹,

Prakash²

2018

IJET

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Subthreshold Swing (SS) of MOSFETs, which determines the low voltage operation of portable mobile devices, cannot reduce below 60mV/dec that restricts MOSFETs for ultra-low power applications. This work presents design and implementation of high ON current, improved Miller capacitance and reduced Subthreshold Swing heterojunction tunneling transistors (HETTs) for portable electronic systems. The performance of HETT with MOSFET has been compared. In this work, the overlapping of gate/oxide on to source can increase the band to band tunneling (BTBT) and improves the ON current of the transistor. Miller capacitance effect can be reduced by the use of low band offset materials and low energy states of materials like Ge or SiGe. This, in turn, results in better performance characteristics for the transistor.The Proposed design and implementation of HETT include both N-type HETT (NHETT) and P-type HETT (PHETT) fabrications and the performance characteristics analysis of both NHETT and PHETT are provided. The advantages and limitations of both NHETT and PHETT for beyond CMOS technologies, in addition to the basic and structural differences between HETTs and conventional MOSFETs to facilitate the use of HETT in place of MOSFET have been elaborated in detail. The construction process of HETT is not at all completely different which is suitable to MOS Design process and is applicable for portable mobile applications. The power analysis of HETT based standard 6T SRAM cell is provided and the performance is verified with the conventional MOSFET based 6T SRAM cell.

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Simulations on 130 nm technology 6T SRAM cell for Near-Threshold operation

Cited by 9 publications

References 7 publications

Design solutions for a low-power SoC platform using near-threshold voltages

Design solutions for a low-power SoC platform using near-threshold voltages

Comparison of 130 nm technology 6T and 8T SRAM cell designs for Near-Threshold operation

Design and Analysis of Heterojunction Tunneling Transistor (HETT) based Standard 6T SRAM Cell

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