Power consumption is an important aspect of almost any electrical device design. Near-Threshold Computing (NTC) is a voltage scaling technique that makes it possible to reduce the power consumption of CMOS devices with the cost of speed and reliability. We are using NTC to design low-power cache memory circuit for a low-performance sensor-based system. Caches consume noteworthy portions of power and area of this kind of systems, and therefore reducing their power consumption has a meaningful impact on the overall power consumption of the whole system. In this paper, 8T SRAM and 6T SRAM memory cells are compared in order to establish guidelines for choosing SRAM cell constructions for NTC systems. 8T SRAM is traditionally concerned as a more reliable memory cell, but we have managed to design 6T SRAM which executes read operation with an acceptaple reliability; read being the most vulnerable operation of conventional 6T SRAM cell. Also, our 6T SRAM cell has 31 % smaller area and smaller power consumption.

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In the future the number of small sensor-based devices is going to increase. The Internet-of-Everything (IoE) vision brings smart miniature electronic devices to objects surrounding our everyday lives. These devices are going to monitor our environment or ourselves. They are also going to execute small tasks based on their observations. Operations of this kind can be done with small low-performance devices. In this paper we present building blocks for a low-power system for sensorbased applications. Our work is aiming for reliable operation with supply voltage of 0.5 V instead of the nominal of 1.2 V. We describe low-power solutions used in 130 nm CMOS technology microprocessor, memory and clock generator. Depending on the component, we have managed to achieve reliable operation with voltages of 0.5-0.8 V. Power consumption of components reduce significantly when operating voltage is scaled down to nearthreshold region.