Simultaneous short-path and long-path timing optimization for FPGAs

Fung, Ryan; Betz, Vaughn; Chow, William

doi:10.1109/iccad.2004.1382691

Cited by 21 publications

(16 citation statements)

References 7 publications

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“…The target delay is highly skewed towards the minimum delay budget -D TARGET will be at most 0.1 ns above D BUDGET_MIN . Our earlier approach in [16] was less aggressive, and only ensured D TARGET would be within 1 ns of D BUDGET_MIN . This change is possible because the minimum delay budget already reflects a path-timing guardband (Section IV.A.4), so minimal additional margin is needed.…”

Section: Delay Portion Of the Routing Costmentioning

confidence: 99%

“…In [16], we described an earlier version of the Routing Cost Valleys (RCV) algorithm. In this paper, we describe the RCV algorithm in more detail, and present significant algorithm enhancements, most notably path-level guardbanding (in Section IV.A.4) and a revised routing delay cost formulation (in Section IV.B.1).…”

Section: Long-path and Short-path Timing Optimizationmentioning

confidence: 99%

“…In this paper, we describe the RCV algorithm in more detail, and present significant algorithm enhancements, most notably path-level guardbanding (in Section IV.A.4) and a revised routing delay cost formulation (in Section IV.B.1). These changes reduce CPU time, improve timing closure on difficult cases, and reduce the additional routing wire needed to repair short-path violations by a factor of 3 to 7 on average (depending on the types of timing constraints) versus that described in [16]. The experimental results have been completely re-done with a more recent version of the Quartus II CAD system, and are more extensive, incorporating both additional experiments and results for the more recent Stratix II FPGAs.…”

Section: Long-path and Short-path Timing Optimizationmentioning

confidence: 99%

“…When it drops below 800 ps, the iterations terminate because very little progress is being made. Stopping iterations when either of these two conditions is satisfied reduces the run-time for slack allocation by nearly 50% versus using the first stopping condition alone, without affecting result quality [16]. Consequently, slack allocation averages less than 6% of the placement-and-routing time, even when the CAD tool is optimizing challenging setup-and-hold constraints (as described in Section V.A.3), which is the most CPU-intensive mode.…”

Section: Basic Algorithmmentioning

confidence: 99%

“…It shows the performance of RCV on these PCI cores without the pathlevel guardbanding technique described in Section IV.A.4. For these results, only connection-level delay budget margin is used to guide the router, as described in [16]. Even though that approach aims for balanced long-path and short-path margin on a connection-basis, with up to 1 ns of short-path margin per connection, 62% of the designs have less than 500 ps of short-path margin and 39% of the designs have less than 500 ps of long-path margin.…”

Section: B Pci Coresmentioning

confidence: 99%

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Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations

Fung¹,

Betz²,

Chow³

2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This work presents the first published algorithm to simultaneously optimize both short-and long-path timing constraints in a Field-Programmable Gate Array (FPGA): the Routing Cost Valleys (RCV) algorithm. RCV consists of two components: a new slack allocation algorithm that determines both a minimum and a maximum delay budget for each circuit connection, and a new router that strives to meet and, if possible, surpass these connection delay constraints. RCV improves both long-path and short-path timing slack significantly versus an earlier Computer-Aided Design (CAD) system, showing the importance of an integrated approach that simultaneously optimizes both types of timing constraints. It is able to meet longpath and short-path timing on all 157 Peripheral Component Interconnect (PCI) cores tested, while an earlier algorithm failed to achieve timing on 75% of the cores. Even in cases where there are no short-path timing constraints, RCV outperforms a stateof-the-art FPGA router and improves the maximum clock speed of circuits by an average of 3.2% (and up to 24.7%).

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Section: Delay Portion Of the Routing Costmentioning

confidence: 99%

Section: Long-path and Short-path Timing Optimizationmentioning

confidence: 99%

Section: Long-path and Short-path Timing Optimizationmentioning

confidence: 99%

Section: Basic Algorithmmentioning

confidence: 99%

Section: B Pci Coresmentioning

confidence: 99%

See 3 more Smart Citations

Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations

Fung¹,

Betz²,

Chow³

2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Droplet Routing in the Synthesis of Digital Microfluidic Biochips

Hwang

Chakrabarty

2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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same level of system-level CAD support that is now commonplace in the IC industry.Recent advances in microfluidics are expected to lead to sensor systems for high-throughput biochemical analysis. CAD tools are needed to handle increased design complexity for such systems. Analogous to classical VLSI synthesis, a top-down design automation approach can shorten the design cycle and reduce human effort. We focus here on the droplet routing problem, which is a key issue in biochip physical design automation. We develop the first systematic droplet routing method that can be integrated with biochip synthesis. The proposed approach minimizes the number of cells used for droplet routing, while satisfying constraints imposed by throughput considerations and fluidic properties. A real-life biochemical application is used to evaluate the proposed method.

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