No abstract

An analytic procedure for calculating vertical fracture extent in symmetrical trilayered formations was extended to multilayered, asymmetrical formations using a semianalytic technique. The fracture extents computed by this method were compared with those calculated with the finite-element method. It was found that even for modulus variations between layers as large as a factor of 5, the semianalytic procedure gave exactly the same results as the finite-element solution in a fraction of the computation time and with significantly less manual data manipulation. It is recommended that the analytic and numerical procedures be used in a complementary manner to calculate fracture-width profiles in layered formations.

Abstract

One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywhere from 50 to 200 man-years simply in the layout step. To date, automated tools have only been employed in small parts of the periphery and programming circuitry. The core tiles, which are repeated many times, are subject to painstaking manual design and layout. In this paper we present a new system (called GILES, for Good Instant Layout of Erasable Semiconductors) that automatically generates a transistor-level schematic from a high-level architectural specification of an FPGA. It also generates a cell-level netlist that is placed and routed automatically. The architectural specification is the one used as input to the VPR [3] architectural exploration tool. The output is the mask-level layout of a single tile that can be replicated to form an FPGA array. We describe a new placement tool that simultaneously places and compacts the layout to minimize white space and wiring demand, and a special-purpose router built for this task. GILES can place and route a tile consisting of four 4-input LUT logic cells and all of its programmable wires in a 0.18µm CMOS process using 8 layers of metal and 25983µm 2 of area. When we generate the layout of an architecture similar to the Xilinx Virtex-E FPGA (built in a 0.18µm process) GILES requires only 47% more area than the original. The layout area of an architecture similar to the Altera Apex 20K400E (also built in a 0.18µm process) constructed by GILES requires 97% more area than the original.

Abstract-This work presents the first published algorithm to simultaneously optimize both short-and long-path timing constraints in a Field-Programmable Gate Array (FPGA): the Routing Cost Valleys (RCV) algorithm. RCV consists of two components: a new slack allocation algorithm that determines both a minimum and a maximum delay budget for each circuit connection, and a new router that strives to meet and, if possible, surpass these connection delay constraints. RCV improves both long-path and short-path timing slack significantly versus an earlier Computer-Aided Design (CAD) system, showing the importance of an integrated approach that simultaneously optimizes both types of timing constraints. It is able to meet longpath and short-path timing on all 157 Peripheral Component Interconnect (PCI) cores tested, while an earlier algorithm failed to achieve timing on 75% of the cores. Even in cases where there are no short-path timing constraints, RCV outperforms a stateof-the-art FPGA router and improves the maximum clock speed of circuits by an average of 3.2% (and up to 24.7%).