Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations

Fung, Ryan; Betz, Vaughn; Chow, William

doi:10.1109/tcad.2008.917585

Cited by 13 publications

(11 citation statements)

References 14 publications

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“…For shadow registers, we care about the critical-path at the slow corner only. Fung et al [7] describe a slack reallocation method to optimise both short paths (MINDELAY) and long paths (MAXDELAY) simultaneously on a regular routing algorithm, in order to meet hold and setup time constraints -this is the method reportedly used by Altera tools.…”

Section: Delay-bounded Routingmentioning

confidence: 99%

Delay-Bounded Routing for Shadow Registers

Hung

Levine

Stott

et al. 2015

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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The on-chip timing behaviour of synchronous circuits can be quantified at run-time by adding shadow registers, which allow designers to sample the most critical paths of a circuit at a different point in time than the user register would normally. In order to sample these paths precisely, the path skew between the user and the shadow register must be tightly controlled and consistent across all paths that are shadowed. Unlike a custom IC, FPGAs contain prefabricated resources from which composing an arbitrary routing delay is not trivial. This paper presents a method for inserting shadow registers with a minimum skew bound, whilst also reducing the maximum skew. To preserve circuit timing, we apply this to FPGA circuits post place-and-route, using only the spare resources left behind. We find that our techniques can achieve an average STA reported delay bound of ±200ps on a Xilinx device despite incomplete timing information, and achieve <1ps accuracy against our own delay model.

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Section: Delay-bounded Routingmentioning

confidence: 99%

Delay-Bounded Routing for Shadow Registers

Hung

Levine

Stott

et al. 2015

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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“…The most common forms of long-and short-path timing violations come from requirements on data paths between registers, inputsetup requirements, and clock-to-output requirements. The problem of solving long-path timing violations has received the vast majority of attention in past research [2]. However, in industry we must also solve the problem of short-path timing violations to guarantee functionality of routed designs.…”

Section: Introductionmentioning

confidence: 99%

“…In [2], a method is proposed to simultaneously solve longand short-path timing issues using specific delay window routing. This approach uses the technique of slack allocation proposed in [3][4] [5] to calculate appropriate delay window bounds on each connection such that the connection will be free of long-and short-path violations.…”

Section: Introductionmentioning

confidence: 99%

“…As with most routing algorithms, searching for a path from a source node to a target node is accomplished using a wavelike search, using costs associated with routing resources to determine an optimal path. For a single wave search, as is implemented in [2], the delay cost function is based on the known delay from the source node to the current wave node, plus the estimated delay from the current wave node to the target node.…”

Section: Introductionmentioning

confidence: 99%

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Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs

Wegley

Zhang

2015

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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In addition to optimizing for timing performance and routability, commercial FPGA routing engines must also support various timing constraints enabling the designer to fine tune aspects of their design. The many intricacies of commercial FPGA architectures add difficulty to the problem of supporting such constraints.In this paper, we show how the method of specific delay window routing can be applied to optimize for these various timing constraints constituting both long-and short-path requirements. Additionally, we enhance existing methods of routing according to specified delay by using dual wave expansion instead of single wave expansion with target delay estimation in order to improve accuracy and support sparser, more varied interconnect structures. Our results show that specific delay window routing is well-suited for optimization targeting a variety of timing constraints, and that using dual wave expansion to eliminate the estimation part of the router's delay cost function enables the router to support tighter timing constraints. For a suite of designs with known hold timing violations, we found that the dual wave approach can correct all such violations, whereas the single wave approach failed to correct the hold timing violations for several designs. Furthermore, for a suite of designs with maximum skew constraints of 250 ps on certain nets and buses, the dual wave approach met the constraints for all designs, whereas the single wave approach failed to meet the constraints for a majority of the designs.

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“…Sarrafzadeh et al [17] present a convex programming based delay budgeting algorithm and use the budgeting results as net length constraints for placement. Fung et al [18] present a slack allocation algorithm which computes both lower and upper bounds of the delay budget for each circuit connection, and then applies the resulting delay budget in a router for timing improvement. Luo et al [19] propose linear programming based placement, geometric programming based gate sizing and multi-V th cell swapping algorithms to achieve power reduction.…”

Section: Introductionmentioning

confidence: 99%

Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography

Jeong¹,

Kahng²

2009

2009 Asia and South Pacific Design Automation Conference

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Abstract-This paper revisits and extends a general linear programming (LP) formulation to exploit multiple knobs such as multi-L gate footprint-compatiblelibrariesandpost-layoutL gatebiasing to minimize total leakage power under timing constraints. We minimize positive timing slack for each cell according to its leakage vs. delay sensitivity, so that unnecessary leakage power consumption is saved without degrading circuit performance. A key difference between our work and previous works is that we pre-process timing libraries to estimate the linear relation -in every slew-load condition -between the gate delay and gate length by linear fitting; we then optimize total leakage power by estimating the optimal gate length for each gate using fast linear programming. With a 65GP industry testbed, and directly comparing with commercial tools, we show the QOR and runtime advantages of our method for the multi-L gate and L gate -biasing knobs. We also show a promising application to circuit timing legalization, a problem which frequently arises when implementation and signoff timers differ. Overall, our results show strong viability of LP based estimation and optimization: compared with the commercial tools, we: (1) shift the achievable delay-leakage tradeoff curve in a positive way, and(2)moreaccuratelymaintainprescribedtimingconstraints.

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Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations

Cited by 13 publications

References 14 publications

Delay-Bounded Routing for Shadow Registers

Delay-Bounded Routing for Shadow Registers

Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs

Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography

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