Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography

Abstract

Abstract-This paper revisits and extends a general linear programming (LP) formulation to exploit multiple knobs such as multi-L gate footprint-compatiblelibrariesandpost-layoutL gatebiasing to minimize total leakage power under timing constraints. We minimize positive timing slack for each cell according to its leakage vs. delay sensitivity, so that unnecessary leakage power consumption is saved without degrading circuit performance. A key difference between our work and previous works is that we pre-process timing libraries to estimate the linear relation -in every slew-load condition -between the gate delay and gate length by linear fitting; we then optimize total leakage power by estimating the optimal gate length for each gate using fast linear programming. With a 65GP industry testbed, and directly comparing with commercial tools, we show the QOR and runtime advantages of our method for the multi-L gate and L gate -biasing knobs. We also show a promising application to circuit timing legalization, a problem which frequently arises when implementation and signoff timers differ. Overall, our results show strong viability of LP based estimation and optimization: compared with the commercial tools, we: (1) shift the achievable delay-leakage tradeoff curve in a positive way, and(2)moreaccuratelymaintainprescribedtimingconstraints.

Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures

“…The work of [13] points out new 'bimodal' performance analysis and design optimization challenges arising from the two CD populations in double patterning. The existence of the two independent CD populations within a die takes away the presumptions of spatial correlation that have always been used to reduce pessimism in timing closure; this causes unpredictable clock skew and timing slack problems.…”

“…This can be solved by recoloring of conflicting cells or shifting cells with the help of whitespaces [13] so as to not cause coloring conflicts. A problem is that placement perturbation at the post-route stage or at near the signoff stage can always introduce new timing violations due to the changes in parasitic RC from ECO routing, unless the placement and routing changes are very localized.…”

“…The existence of the two independent CD populations within a die takes away the presumptions of spatial correlation that have always been used to reduce pessimism in timing closure; this causes unpredictable clock skew and timing slack problems. The authors of [13] analyze delay variation of a timing path consisting of cell instances that can have differing delay variations due to the bimodal CD distribution. The delay variation of the timing path is calculated as the sum of variances of the delay value of each cell and the covariances between the delay values of different cells.…”

“…However, DPL gives rise to two independent, uncorrelated distributions of linewidth on a chip, resulting in a 'bimodal' linewidth distribution and an increase in performance variation. [13] suggested that new physical design mechanisms could reduce harmful covariance terms that contribute to this performance variation.…”

“…However, DPL gives rise to two independent, uncorrelated distributions of linewidth on a chip, resulting in a 'bimodal' linewidth distribution and an increase in performance variation. [13] suggested that new physical design mechanisms could reduce harmful covariance terms that contribute to this performance variation.In this paper, we propose new bimodal-aware timing analysis and optimization methods to improve timing yield of standardcell based designs that are manufactured using DPL. Our first contribution is a DPL-aware approach to timing modeling, based on detailed analysis of cell layouts.…”