Crosshairs SRAM — An adaptive memory for mitigating parametric failures

Abstract

We propose Crosshairs SRAM to adaptively fix parametric failures and increase yield. It mitigates process variation by tuning VDD and GND of each bitcell inverter independently from its cross-coupled counterpart. It targets failing cells at the intersection of individually-tuned orthogonal VDD and GND rails. We implement 70 32kb test arrays in 45nm CMOS with little modification to a commercial 6T design and no increase in bitcell area. Crosshairs improves performance by 13% and fixes an average of 70% of parametric failures for reasonable initial failure rates lower than 0.1%.

A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM

“…As an essential part of SoC, random static memory (SRAM) accounts for up to 50% of the area in SoC [1]. Therefore, the power consumption problem caused by SRAM cannot be ignored [2,3,4]. Lowering the supply voltage is the most effective way to reduce power consumption [5,6,7].…”