Automatic transistor and physical design of FPGA tiles from an architectural specification

Abstract

One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywhere from 50 to 200 man-years simply in the layout step. To date, automated tools have only been employed in small parts of the periphery and programming circuitry. The core tiles, which are repeated many times, are subject to painstaking manual design and layout. In this paper we present a new system (called GILES, for Good Instant Layout of Erasable Semiconductors) that automatically generates a transistor-level schematic from a high-level architectural specification of an FPGA. It also generates a cell-level netlist that is placed and routed automatically. The architectural specification is the one used as input to the VPR [3] architectural exploration tool. The output is the mask-level layout of a single tile that can be replicated to form an FPGA array. We describe a new placement tool that simultaneously places and compacts the layout to minimize white space and wiring demand, and a special-purpose router built for this task. GILES can place and route a tile consisting of four 4-input LUT logic cells and all of its programmable wires in a 0.18µm CMOS process using 8 layers of metal and 25983µm 2 of area. When we generate the layout of an architecture similar to the Xilinx Virtex-E FPGA (built in a 0.18µm process) GILES requires only 47% more area than the original. The layout area of an architecture similar to the Altera Apex 20K400E (also built in a 0.18µm process) constructed by GILES requires 97% more area than the original.

Fast prototyping environment for embedded reconfigurable units

“…One of the most famous ADL-based tool for FPGA is GILES [15]. This tool is able to generate an FPGA layout from a VPR description of the architecture [16].…”

Design space exploration for application specific FPGAS in system-on-a-chip designs

“…In [1], FPGA specific standard cells are proposed to enable more efficient implementation of FPGAs within standard cell technologies by imposing structure specific to the FPGA. In [7] and [10], researchers present a method for automatically generating a transistor level implementation of an FPGA starting from an architectural description of the FPGA with only a 36% area overhead compared to a full-custom implementation and have verified their automated process with the successful fabrication of the resulting FPGA implementation. In [4][5] [6], Holland and Hauck presented an automated tool flow for creating domain-specific PLAs, PALs, and CPLDs.…”

Generic Techniques and CAD tools for automated generation of FPGA Layout

“…It is reported in [3] that a new FPGA creation involves approximately 50 to 200 person years, thus increasing the overall time to market of the final product. It is an interesting option to significantly reduce the time-to-market of the product at the expense of limited area penalty.…”

“…A number of previous attempts have been made regarding automated generation of FPGAs. One of the major works in this domain is done in [6] [3]. They have demonstrated the complete automation of FPGA creation with significantly reduced manual labor.…”

“…They have demonstrated the complete automation of FPGA creation with significantly reduced manual labor. The GILES [3] tools are used to generate different tiles which are then abutted together to form a complete FPGA. The clock and power segments are later routed using SKILL [7].…”