Single event multiple transient (SEMT) measurements in 65 nm bulk technology

Evans, Adrian; Glorieux, Maximilien; Alexandrescu, Dan; Polo, Cesar Boatella; Ferlet-Cavrois, V.

doi:10.1109/radecs.2016.8093192

Cited by 21 publications

(11 citation statements)

References 15 publications

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“…The works in [20,21] are based on probabilistic models and statistical methods for SER estimation. However, modern chips tend to be more vulnerable to high-energy particle strikes due to the technology downscaling and, thus, the reduction in the distance among the cells has increased the occurence of multiple transient faults (MTFs) caused by a single particle strike [22][23][24][25][26]. Therefore, recently, research in the particular field focuses on the SER evaluation in the presence of single event multiple transients (SEMTs).…”

Section: Related Workmentioning

confidence: 99%

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SET Pulse Characterization and SER Estimation in Combinational Logic with Placement and Multiple Transient Faults Considerations

et al. 2020

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Integrated circuit susceptibility to radiation-induced faults remains a major reliability concern. The continuous downscaling of device feature size and the reduction in supply voltage in CMOS technology tend to worsen the problem. Thus, the evaluation of Soft Error Rate (SER) in the presence of multiple transient faults is necessary, since it remains an open research field. In this work, a Monte-Carlo simulation-based methodology is presented taking into consideration the masking mechanisms and placement information. The proposed SER estimation tool exploits the results of a Single Event Transient (SET) pulse characterization process with HSPICE to obtain an accurate assessment of circuit vulnerability to radiation. A new metric, called Glitch Latching Probability, which represents the impact of the masking effects on a SET, is introduced to identify gate sensitivity and, finally, experimental results on a set of ISCAS’ 89 benchmarks are presented.

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Section: Related Workmentioning

confidence: 99%

“…Therefore, recently, research in the particular field focuses on the SER evaluation in the presence of single event multiple transients (SEMTs). In [23], heavy-ion experiments are conducted to characterize the SEMTs. In [26,27], the authors introduce the identification of the cell sensitive regions for SER estimation.…”

Section: Related Workmentioning

confidence: 99%

SET Pulse Characterization and SER Estimation in Combinational Logic with Placement and Multiple Transient Faults Considerations

et al. 2020

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“…As process feature sizes continue to shrink, clock frequencies continue to increase, node capacitance and supply voltage decrease, the critical charge of transient pulses is reduced [3][4][5], and waveforms are more easily captured and soft errors are formed. It has been reported that SET are the main cause of soft errors in space applications [6,7], and charge sharing may even affect multiple nodes and cause single-event multiple transients (SEMT) [8][9][10]. These problems are already common in combinatorial logic circuits.…”

Section: Introductionmentioning

confidence: 99%

“…The load resistance and line capacitance of the test system cause large pulse distortion, and the on-chip measurement is believed to be a better solution in most applications, and Narasimham et al [20] invented a self-triggering technique for measuring SET pulses in 130 nm and 90 nm chips in Reference [12]. In other processes, there are also examples [3,9,13,14] of successful use of this measurement method. On the basis of this method, Huang et al [8] proposed a structure that can simultaneously measure multiple transient pulses, using eight capture circuits to share a self-trigger structure design, which can measure the SEMT.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain

Liang

Chi

et al. 2020

Symmetry

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The reliability of integrated circuits under advanced process nodes is facing more severe challenges. Single-event transients (SET) are an important cause of soft errors in space applications. The SET caused by heavy ions in the 28 nm bulk silicon inverter chains was studied. A test chip with good symmetry layout design was fabricated based on the 28 nm process, and the chip was struck by using 5 kinds of heavy ions with different linear energy transfer (LET) values on heavy-ion accelerator. The research results show that in advanced technology, smaller sensitive volume makes SET cross-section measured at 28 nm smaller than 65 nm by an order of magnitude, the lower critical charge required to generate SET will increase the reliability threat of low-energy ions to the circuit, and high-energy ions are more likely to cause single-event multiple transient (SEMT), which cannot be ignored in practical circuits. The transients pulse width data can be used as a reference for SET modeling in complex circuits.

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“…This was less of a concern in old CMOS technologies where single particles only affected single digital cells. However, as technologies have scaled down, Multi-Bit Upsets (MBU) have become a serious concern such that one particle can affect multiple gates simultaneously [10][11][12]. With improper placement, the fault tolerance can dramatically reduce, especially in fast designs.…”

Section: Introductionmentioning

confidence: 99%

Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

2019

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This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

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Single event multiple transient (SEMT) measurements in 65 nm bulk technology

Cited by 21 publications

References 15 publications

SET Pulse Characterization and SER Estimation in Combinational Logic with Placement and Multiple Transient Faults Considerations

SET Pulse Characterization and SER Estimation in Combinational Logic with Placement and Multiple Transient Faults Considerations

Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain

Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

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