Single-Event Response of 22-nm Fully Depleted Silicon-on-Insulator Static Random Access Memory

Casey, Megan C.; Stansberry, Scott D.; Seidleck, C.M.; Maharrey, J. A.; Gamboa, Dante; Pellish, Jonathan A.; LaBel, Kenneth A.

doi:10.1109/tns.2021.3060365

Cited by 10 publications

(3 citation statements)

References 18 publications

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“…Table III shows the model parameters for the 22-nm SOI SRAM being examined (different from Table II for the 65-nm SOI SRAM). As shown, d SOI is explicitly given in the article that reports σ examined here [19]. We estimated A and V DR from an article [28] that reports a similar 22-nm SOI SRAM, which was fabricated by the same manufacturer as the part being examined.…”

Section: B 22-nm Soi Srammentioning

confidence: 99%

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An SRAM SEU Cross Section Curve Physics Model

Kobayashi

Hirose

Sakamoto

et al. 2022

IEEE Trans. Nucl. Sci.

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Static random access memories (SRAMs) are prone to a single-event upset (SEU), also known as soft errors, due to transient noise caused by a single strike of radiation. Beam testing has been extensively used to measure the SEU cross section of SRAMs as a function of the linear energy transfer (LET) of charged particle radiation. The evolution of the cross section as a function of LET is called the cross section curve, which plays a vital role in upset rate analysis for hardness assurance. Various analytical models have been developed to describe SRAM SEU cross section curves, and they have proven to be useful in reducing the cost of beam testing as well as revealing the physics behind test results. However, they involve arbitrary parameters, which make it challenging to predict cross section curves without any beam results. Moreover, the current method of analyzing cross section curves or the LET dependence of cross sections relies on a model different from that is used in the analysis of power-supplyvoltage dependence, which is becoming increasingly important because of the demand for low-power operation. To overcome these problems, this article proposes a unified equation that describes both LET and the power-supply-voltage dependence of SRAM SEU cross sections. It comprises only parameters that are physically clear and familiar to SEU researchers. As well as giving possible constraints, comparisons with data from the literature suggest it can be applied to SRAMs fabricated in bulk and silicon-on-insulator (SOI) processes across generations from the early 1000-nm-scale to the current 10-nm-scale technology nodes.

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Section: B 22-nm Soi Srammentioning

confidence: 99%

“…Cross section curves of the 22-nm SOI SRAM (case B). The measurement results (symbols) are taken from [19,Fig. 10].…”

Section: -Nm Soi Srammentioning

confidence: 99%

An SRAM SEU Cross Section Curve Physics Model

Kobayashi

Hirose

Sakamoto

et al. 2022

IEEE Trans. Nucl. Sci.

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“…With the rapid progress of integrated circuit technology, the device feature size and supply voltage gradually decrease, resulting in a continuous decrease in the critical charge of SRAM cells [ 1 , 2 ]. There are a large number of high-energy particles in the space environment, and the running SRAM circuit is highly susceptible to the impact of high-energy particles, which can induce single-event upset (SEU) effects [ 3 ].…”

Section: Introductionmentioning

confidence: 99%

A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications

Yao

Zhang

et al. 2023

Micromachines

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The static random-access memory (SRAM) cells used in the high radiation environment of aerospace have become highly vulnerable to single-event effects (SEE). Therefore, a 12T SRAM-hardened circuit (RHB-12T cell) for the soft error recovery is proposed using the radiation hardening design (RHBD) concept. To verify the performance of the RHB-12T, the proposed cell is simulated by the 28 nm CMOS process and compared with other hardened cells (Quatro-10T, WE-Quatro-12T, RHM-12T, RHD-12T, and RSP-14T). The simulation results show that the RHB-12T cell can recover not only from single-event upset caused by their sensitive nodes but also from single-event multi-node upset caused by their storage node pairs. The proposed cell exhibits 1.14×/1.23×/1.06× shorter read delay than Quatro-10T/WE-Quatro-12T/RSP-14T and 1.31×/1.11×/1.18×/1.37× shorter write delay than WE-Quatro-12T/RHM-12T/RHD-12T/RSP-14T. It also shows 1.35×/1.11×/1.04× higher read stability than Quatro-10T/RHM-12T/RHD-12T and 1.12×/1.04×/1.09× higher write ability than RHM-12T/RHD-12T/RSP-14T. All these improvements are achieved at the cost of a slightly larger area and power consumption.

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