2001 IEEE Radiation Effects Data Workshop. NSREC 2001. Workshop Record. Held in Conjunction With IEEE Nuclear and Space Radiati
DOI: 10.1109/redw.2001.960445
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Single event upset characterization of the Pentium(R) MMX and low power Pentium(R) MMX microprocessors using proton irradiation

Abstract: Experimental single event upset characterization of the Pentiurn@ MMX a.nd Low Power Pentiurn@ MMX microprocessors using proton irradiation is presented. Results are compared with previous tests on the Pentiurn@ MMX, Pentiurn@ 11, and Celerm@.

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Cited by 8 publications
(18 citation statements)
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“…It has a transistor count of 29 million, operates at 1.7 Vdc and has 16 kbyte of L1 code and data cache plus 256 kbyte of L2 cache, ECC protected, on the die [12]. The LPMMX (rated for 266 MHz operation), tested at 166 MHz in this paper and 266 MHz previously [4], was manufactured on a 0.25 µm gate length CMOS process. It has a transistor count of 4.5 million, operates at 2.0Vdc and has 16 kbyte of L1 code and data cache on the die [13].…”
Section: Proton Irradiationmentioning
confidence: 99%
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“…It has a transistor count of 29 million, operates at 1.7 Vdc and has 16 kbyte of L1 code and data cache plus 256 kbyte of L2 cache, ECC protected, on the die [12]. The LPMMX (rated for 266 MHz operation), tested at 166 MHz in this paper and 266 MHz previously [4], was manufactured on a 0.25 µm gate length CMOS process. It has a transistor count of 4.5 million, operates at 2.0Vdc and has 16 kbyte of L1 code and data cache on the die [13].…”
Section: Proton Irradiationmentioning
confidence: 99%
“…The MMX's (rated for 233 MHz operation), tested at 233 MHz and 200 MHz previously [2,3,4], were manufactured on a 0.35 µm gate length CMOS process. It has a transistor count of 4.5 million, operates at 2.8 Vdc and has 16 kbyte of L1 code and data cache on die [14].…”
Section: Proton Irradiationmentioning
confidence: 99%
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