Single Photon Avalanche Detectors in Standard CMOS

Abstract

We report an improved design and successful demonstration of single photon avalanche diode (SPAD) detectors fabricated in a standard nwell 0.5 µm CMOS technology.The detectors are implemented as circular junctions between p+ and nwell regions. Two techniques are used to suppress perimeter breakdown: guard rings at the edges of the junctions, formed using lateral diffusion of adjacent nwell regions, and a poly-silicon control gate over the diffused guard rings and surrounding regions. The detectors exhibit a breakdown voltage of -16.85 V, ~4 V higher than simple diode structures in the same technology. The detector exhibits a thermal event rate of 16000 counts/s at room temperature at an excess bias voltage of 1.15 V.

Characterization of Single-Photon Avalanche Diodes in a 0.5 $\mu$m Standard CMOS Process—Part 1: Perimeter Breakdown Suppression

“…Pauchard et al have shown a CMOS compatible process for fabricating a photodiode with reduced perimeter breakdown; the device comprised a field limiting guard ring placed at a distance from the implant in conjunction with a control gate over the gap [19]. We have previously shown the combination of the lateral diffusion of n-wells, similar in spirit to that demonstrated by Rochas et al, in combination with a depletion gate to further reduce premature edge breakdown [20]. All of these techniques stem from original works by Grove et al and Temple et al who studied the effects of dopant concentration modulation and junction curvature on the breakdown voltage [17], as well as the effects of field plates over high field regions [21].…”

“…This paper focuses solely on the device's breakdown characteristics; we will consider its Geiger mode operation in a later publication (Part 2). For preliminary work showing Geiger mode operation of the device described herein, see [20], [30].…”

An analysis of the information efficiency of single photon avalanche diodes

“…This results in poor photon detection efficiency and thus ultimately poor performance. One solution is to apply a potential at a polysilicon control gate which is drawn over the edges of a SPAD [12]. This provides another independent design variable which must be considered.…”

Fully Integrated Linear Single Photon Avalanche Diode (SPAD) Array with Parallel Readout Circuit in a Standard 180 nm CMOS Process

“…The active SPAD device is made inside an n-well, which acts as the cathode and the anode is formed by p+ diffusions. A low doped guard ring formed by diffusion or well layers has been introduced and reduced edge effects were reported by Rochas et al, Marwick et al and Dandin et al [1,12,13,17]. In Geiger mode, the electron-holes pairs generated due to the absorption of an incident light in the p+ diffusion area (anode) are multiplied before collected by n+ terminal (cathode) [19].…”