Single-Port SRAM-Based Transpose Memory With Diagonal Data Mapping for Large Size 2-D DCT/IDCT

Shang, Qing; Fan, Yibo; Sui, Weiwei; Shen, S. C.; Zeng, Xiaoyang

doi:10.1109/tvlsi.2013.2295116

Cited by 21 publications

(10 citation statements)

References 9 publications

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“…This makes it a key component for the 2D fast Fourier transform (FFT) in image processing and machine vision [1], multiple-input multipleoutput (MIMO) [2], [3], automotive [4] and synthetic aperture radars [5]- [7]. Likewise, it is required for the 3D FFT in molecular dynamics [8], motion detection [9]; for the 2D discrete cosine transform (DCT) in image compression [10], [11]; for the 2D fast Hartley transform (FHT) in image processing and circular convolution [12], [13]; and for the 3D fast Wavelet transform (FWT) in video encoding [14]. Additionally, matrix transposition is considered in convolutional neural networks (CNN) [15], [16] for artificial intelligence.…”

Section: Introductionmentioning

confidence: 99%

“…One of the memories stores and transposes the even matrices in the flow and the other one handles the odd ones. More recent techniques improve this approach by making use of a single memory of size N [10], [17], [23], [24].…”

Section: Introductionmentioning

confidence: 99%

“…Second, the access to the memory may be limited. For small data sizes, either registers [25] or small memories that can be read or written arbitrarily may be used [10]. On the contrary, large memories such as a synchronous dynamic random-access memories (SDRAM) [26] are not so easily addressable.…”

Section: Introductionmentioning

confidence: 99%

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Continuous-Flow Matrix Transposition Using Memories

Garrido

Pirsch

2020

IEEE Trans. Circuits Syst. I

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In this paper, we analyze how to calculate the matrix transposition in continuous flow by using a memory or group of memories. The proposed approach studies this problem for specific conditions such as square and non-square matrices, use of limited access memories and use of several memories in parallel. Contrary to previous approaches, which are based on specific cases or examples, the proposed approach derives the fundamental theory involved in the problem of matrix transposition in a continuous flow. This allows for obtaining the exact equations for the read and write addresses of the memories and other control signals in the circuits. Furthermore, the cases that involve non-square matrices, which have not been studied in detail in the literature, are analyzed in depth in this paper. Experimental results show that the proposed approach is capable of transposing matrices of 8192 x 8192 32-bit data received in series at a rate of 200 mega samples per second, which doubles the throughput of previous approaches.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Continuous-Flow Matrix Transposition Using Memories

Garrido

Pirsch

2020

IEEE Trans. Circuits Syst. I

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“…The architecture still consumes large circuit area. Several works present low-cost transpose architecture to deal with the area overhead [14][15][16][17][18]. The multiplexer is used to control the 1-D inverse discrete cosine transform (IDCT) core for the calculation of 1-D and 2-D operations, and the 1-D IDCT core uses matrix decomposition to reduce the required circuit area.…”

Section: Introductionmentioning

confidence: 99%

“…Besides, the transform size can be up to 32 × 32 in HEVC standard; thus, the transpose memory consumes large of circuit area. Several works present low-cost transpose architecture to deal with the area overhead [14][15][16][17][18].…”

Section: Introductionmentioning

confidence: 99%

High‐throughput IDCT architecture for high‐efficiency video coding (HEVC)

Chen

2017

Circuit Theory & Apps

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This paper presents a hardware design capable of supporting high-efficiency video coding inverse discrete cosine transform (IDCT) with a 32 × 32 transform unit size, using a single 1-D IDCT core with transpose memory to reduce costs. The proposed 1-D IDCT core employs 16 computation paths for high throughput and is implemented using distributed arithmetic to facilitate the sharing of hardware resources. The proposed 1-D IDCT is capable of calculating 1-D and 2-D data simultaneously along 32 parallel paths. When implemented using Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm CMOS technology, the proposed 2-D transform core provides throughput of 6.4 gigapixels/s with a gate count of 335 k. The results show that a superior hardware efficiency can be achieved in the proposed 32-point IDCT core compared with the existing works.

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