Sizing Analog Integrated Circuits by Current-Branches-Bias Assignments with Heuristics

Guerra-Gomez, I.; Tlelo‐Cuautle, Esteban

doi:10.5755/j01.eee.19.10.2464

Cited by 13 publications

(3 citation statements)

References 19 publications

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“…Metaheuristics are a good option in the sizing of analog ICs [28][29][30]. One can handle constraints to guide the optimization algorithm to find feasible solutions and also one can identify sets of MOS transistors having the same sizes or scaled values in order to reduce the search spaces of the design variables [18], and to ensure robustness when performing PVT variation analysis [28].…”

Section: Problem Formulation and Handling Of Constraintsmentioning

confidence: 99%

Sizing CMOS Amplifiers by PSO and MOL to Improve DC Operating Point Conditions

2020

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The sizes of the metal-oxide-semiconductor (MOS) transistors in an operational amplifier must guarantee strong direct current operating point (DCOP) conditions. This paper shows the usefulness of two population-based optimization algorithms to size transistors, namely—particle swarm optimization (PSO) and many optimizing liaisons (MOL). Both optimization algorithms link the circuit simulator SPICE to measure electrical characteristics. However, SPICE provides an output-file indicating that a transistor is in strong inversion but the DCOP can be in the limit, and it can switch to a different condition. In this manner, we highlight the application of PSO and MOL to size operational transconductance amplifiers (OTAs), which DCOP conditions are improved by the introduction of a procedure that handles constraints to ensure that the transistors are in the appropriate DCOP. The Miller and RFC-OTA are the cases of study, and their sizing is performed using UMC 180 nm CMOS technology. In both OTAs, the objective function is the maximization of the gain-bandwidth product under the main constraint of guaranteeing DCOPs to improve two figures of merit and to provide robustness to Monte Carlo simulations and PVT variations.

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Section: Problem Formulation and Handling Of Constraintsmentioning

confidence: 99%

Sizing CMOS Amplifiers by PSO and MOL to Improve DC Operating Point Conditions

2020

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“…This section describes the application of the evolutionary algorithms [20][21][22] to compute the optimum size of the MOSFET taking into account the circuit design constraints.…”

Section: Optimal Vco Design Through Evolutionary Algorithmsmentioning

confidence: 99%

Performance enhancement of a VCO using symbolic modelling and optimisation

Panda

Patnaik

Mal

2018

IET Circuits, Devices & Systems

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This study proposed an application of symbolic technique on the characterisation of a ring voltage controlled oscillator (VCO) for optimum performance. Here nullor-based symbolic noise modelling and analysis of the CMOS ring VCO is carried out. Circuit equations are processed through modelling of all the metal-oxide-semiconductor field-effect transistors with their nullor equivalent. The closed-form expressions for the total output noise density and phase noise of VCO are obtained. With this technique, the total output noise density and phase noise calculated are compared with the results obtained from the transistorlevel simulation. From the comparison, it has been observed that the nullor-based modelling and analysis simplifies the noise expression as well as reduces CPU execution time. The performance enhancement of the VCO is carried out using two different optimisation techniques. These are particle swam optimisation and non-dominated sorting genetic algorithm. The results obtained for the optimised VCO are then tested using SPICE. The SPICE result shows a significant improvement in phase noise, power consumption and tuning range for the optimised VCO.

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“…Currently, CMOS (complementary metal-oxide semiconductor) devices are the most popular for RFIC (radio frequency integrated circuit) design due to their low cost [ 1 – 15 ]. In particular, CMOS RFICs can more easily be integrated with other analog or digital ICs than with GaAS (gallium arsenide) RFICs [ 16 – 21 ].…”

Section: Introductionmentioning

confidence: 99%

2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain

Lee

Park

2014

The Scientific World Journal

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We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm2.

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Sizing Analog Integrated Circuits by Current-Branches-Bias Assignments with Heuristics

Cited by 13 publications

References 19 publications

Sizing CMOS Amplifiers by PSO and MOL to Improve DC Operating Point Conditions

Sizing CMOS Amplifiers by PSO and MOL to Improve DC Operating Point Conditions

Performance enhancement of a VCO using symbolic modelling and optimisation

2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain

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