'Smart integrated circuit processing

Fu, Chi Yung; Chang, Norman; Lin, Kevin

doi:10.1109/66.44619

Cited by 9 publications

(1 citation statement)

References 6 publications

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“…Despite its 47 order relations, the cardinality for this graph is approximately kDk 2:6 10 7 . Due to the very large number of processes, additional constraints are added between its three reactive growths reducing kDk 710 5 and its eight di usions kDk 81. The cardinality increases to kDk 860 after the graph modi cation for implant-through layers.…”

Section: Compiler Testingmentioning

confidence: 99%

Process compilation of thin film microdevices

Hasanuzzaman

Mastrangelo

1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper describes a systematic method for the automatic generation of fabrication processes of thin lm devices. The method uses a partially ordered set poset representation of device topology describing the order between its various components in the form of a directed acyclic graph. The sequence in which these components are fabricated is determined from the poset linear extensions, and the component sequence is expanded into a corresponding process ow. The graphtheoretic synthesis method is powerful enough to establish existence and multiplicity o f o ws thus creating a design space D suitable for optimization. The cardinality kDk for a device with N components is large with a worst case kDk N , 1! yielding in general a combinatorial explosion of solutions. The number of solutions is controlled through a-priori estimates of kDk and condensation of the device graph. The method has been implemented in the computer program MISTIC Michigan Synthesis Tools for Integrated Circuits which calculates speci c process parameters using an internal database of process modules and materials. Currently MISTIC includes process modules for deposition, lithography, etching, ion implantation, coupled simultaneous di usions, and reactive growth. The compilation procedure was applied to several device structures. For a double metal twin-well BiCMOS structure, the compiler generated 168 complete process ows.

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Section: Compiler Testingmentioning

confidence: 99%

Process compilation of thin film microdevices

Hasanuzzaman

Mastrangelo

1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Semiconductor Process Representation

Troxel

Boning

McIlrath

1999

Wiley Encyclopedia of Electrical and Electronics Engineering

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The sections in this article are Information Model User and Program Interfaces Process Libraries Application Programs Application: Factory Design Application: Computer Integrated Manufacturing Application: Simulation Standardization

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Creating and using equipment models in semiconductor manufacturing

Spanos

1991

Microelectronic Engineering

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'Smart integrated circuit processing

Cited by 9 publications

References 6 publications

Process compilation of thin film microdevices

Process compilation of thin film microdevices

Semiconductor Process Representation

Creating and using equipment models in semiconductor manufacturing

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