SMI: Slack Measurement Insertion for online timing monitoring in FPGAs

Levine, Joshua M.; Stott, Edward; Constantinides, George A.; Cheung, Peter Y. K.

doi:10.1109/fpl.2013.6645598

Cited by 14 publications

(7 citation statements)

References 5 publications

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“…This gives more upper hand for the proposed dynamic speculation window based error detection method over the classical Razor-based timing error detection. In [14], an online slack measurement technique based on [6], [12], and [13] is used to scale the supply voltage or frequency to increase the energy savings. The output of the path under monitoring (PUM) is sampled by both main register and shadow register using same clock frequency but different phases as shown in Fig.…”

Section: Experiments and Resultsmentioning

confidence: 99%

“…In [6], [12], and [13], online slack measurement techniques are proposed to determine the delay of the combinational components in the pipeline at run time. An additional sampling register is added to the output of the pipeline, which samples the data before the main output register of the pipeline.…”

Section: Slack Measurementmentioning

confidence: 99%

“…An FPGA prototype is used as proof of concept, though the idea can be extended to any type of datapaths. The proposed method is based on doublesampling and online slack measurement [6] to overclock and underclock the design adaptively according to temperature and other variability effects, and therefore to detect and correct timing errors. Addition of buffers for shorter path is not required, since the speculation window is dynamically changed.…”

Section: Introductionmentioning

confidence: 99%

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Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window

Ragavan

Killian

Sentieys

2016

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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International audienceError detection and correction based on double-sampling is used as common technique to handle timing errors while scaling V dd for energy efficiency. An additional sampling element is inserted in the critical paths of the design, to double sample the outputs of those logic paths at different time instances that may fail while scaling the supply voltage or the clock frequency of the design. However, overclocking, and error detection and correction capabilities of the double sampling methods are limited due to the fixed speculation window which lacks adaptability for tracking variations such as temperature. In this paper, we introduce a dynamic speculation window to be used in double sampling schemes for timing error detection and correction in pipelined logic paths. The proposed method employs online slack measurement and conventional shadow flipflop approach to adaptively overclock or underclock the design and also to detect and correct timing errors due to temperature and other variability effects. We demonstrate this method in the Xilinx Virtex VC707 FPGA for various benchmarks. We achieve a maximum of 71% overclocking with a limited area overhead of 1.9% LUTs and 1.7% flip-flops

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Section: Experiments and Resultsmentioning

confidence: 99%

Section: Slack Measurementmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window

Ragavan

Killian

Sentieys

2016

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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“…This is the key technique for achieving Razor [6], a method that speculatively overclocks a circuit (most commonly, CPUs) beyond its rated limits, with the provision that any timing errors are infrequent, detectable, and recoverable. The final mode is when φ offset is swept through a range of values in order to perform on-chip slack measurement by determining the exact point at which each shadowed path starts to fail, and has been used for device characterisation [13]. Bounding the skew for these modes would allow more precise Razor detection, as well as reduce calibration effort during slack measurement.…”

Section: Background and Related Workmentioning

confidence: 99%

“…Prior work on shadow registers [13] relies on standard incremental compilation techniques to insert shadow registers. MINDELAY and MAXDELAY constraints can be applied to (coarsely) bound T skew across all nets, though this can be difficult when each constraint is applied to a different timing corner.…”

Section: Delay-bounded Routingmentioning

confidence: 99%

Delay-Bounded Routing for Shadow Registers

Hung

Levine

Stott

et al. 2015

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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The on-chip timing behaviour of synchronous circuits can be quantified at run-time by adding shadow registers, which allow designers to sample the most critical paths of a circuit at a different point in time than the user register would normally. In order to sample these paths precisely, the path skew between the user and the shadow register must be tightly controlled and consistent across all paths that are shadowed. Unlike a custom IC, FPGAs contain prefabricated resources from which composing an arbitrary routing delay is not trivial. This paper presents a method for inserting shadow registers with a minimum skew bound, whilst also reducing the maximum skew. To preserve circuit timing, we apply this to FPGA circuits post place-and-route, using only the spare resources left behind. We find that our techniques can achieve an average STA reported delay bound of ±200ps on a Xilinx device despite incomplete timing information, and achieve <1ps accuracy against our own delay model.

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