Smooth and high quality epitaxial strained Ge grown on SiGe strain relaxed buffers with 70–85% Ge

Loo, Roger; Souriau, Laurent; Ong, Patrick; Kenis, Karine; Rip, Jens; Storck, P.; Buschhardt, Thomas; Vorderwestner, Martin

doi:10.1016/j.jcrysgro.2011.03.030

Cited by 34 publications

(20 citation statements)

References 17 publications

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“…Another important quality parameter is the cross hatch roughness of the SiGe surface that is caused by the misfit network. Although the roughness can be removed by chemo-mechanical polishing (CMP) prior to further processing [4] the intensity of the cross hatch lines can vary significantly and impact the crystal quality of the SiGe layer.…”

Section: Introductionmentioning

confidence: 99%

(Invited) Epitaxial Growth of Low Defect SiGe Buffer Layers for Integration of New Materials on 300 mm Silicon Wafers

Kozlowski¹,

Fursenko²,

Zaumseil³

et al. 2013

ECS Trans.

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We report on the structural characterization of state-of-the-art SiGe graded buffers on Si(001) substrates with a diameter of 300 mm with and without a backside stressor. The main beneficial effect of the backside stressor is a clear improvement in surface morphology in terms of reduced surface roughness and substantially decreased density of threading dislocation pile-ups all across the wafer. X-ray diffraction furthermore proves that the relaxation of the various layers in the SiGe buffer is triggered by the misfit stress of the subsequently deposited layer. In addition, spatially resolved microRaman studies demonstrate that the formed cross hatch pattern surface morphology is clearly correlated with strain field and not with Ge concentration fluctuations.

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Section: Introductionmentioning

confidence: 99%

(Invited) Epitaxial Growth of Low Defect SiGe Buffer Layers for Integration of New Materials on 300 mm Silicon Wafers

Kozlowski¹,

Fursenko²,

Zaumseil³

et al. 2013

ECS Trans.

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“…Moreover, the region underneath the channel has an n-type doping concentration around 5 × 10 18 cm −3 . The processing details regarding the germanium layer growth for the three considered scenarios, i.e., STI last-strained, STI firststrained, and STI last-relaxed, can be found in [10]- [12], respectively, where Fig. 1 shows the main difference among them.…”

Section: Device Characteristicsmentioning

confidence: 99%

“…In order to keep the TD density as low as possible, different techniques have been evaluated to grow a Ge layer, which can be either on top of a Si-Ge strain relaxed buffer (SRB) [10] or directly on silicon [11]. The first process fabricates SRB layers in predefined shallow trench isolation (STI) region (referred to as STI-first) [12], where the SRB layer must be thick enough, i.e., with an aspect ratio higher than 3, so that most of the TDs are trapped in the bottom part of the layer [13].…”

Section: Introductionmentioning

confidence: 99%

Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes

Oliveira

Simoen

Mitard

et al. 2016

IEEE Trans. Electron Devices

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An experimental low-frequency noise (LFN) assessment of long channel Ge pFinFET devices fabricated in different shallow trench isolation (STI) processes is presented, taking into consideration devices with fin widths from 100 nm (planar-like) down to 20 nm. In addition, the correlation among LFN parameters, hole mobility and threshold voltage, is also evaluated. The carrier number fluctuation (N) model is confirmed as dominant mechanism for all studied Ge pFinFETs and there is no correlation with the used STI process. From the LFN, it is evidenced that the Coulomb scattering mobility mechanism plays an important role for STI-first process, resulting in a mobility degradation.

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“…The in-situ approach permits to avoid an airbreak in between depositions which requires a challenging oxide removal-wet clean of a post CMPed Si 0.5 Ge 0.5 surface (13). Thin SiGe SRB growth: evidence of facets formation Standard 300mm Si STI wafers were loaded in a 300mm ASM Epsilon TM CVD reactor, load locked system.…”

Section: Selective Sige Srb Growth In Sti For Biaxial Compressive Strmentioning

confidence: 99%

Biaxial and Uniaxial Compressive Stress Implemented in Ge(Sn) pMOSFET Channels by Advanced Reduced Pressure Chemical Vapor Deposition Developments

Vincent¹,

Gencarelli²,

Lin³

et al. 2011

ECS Trans.

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Three advanced architectures for ultimate progress in Ge p-Metal Oxide Semiconductor Field Effect Transistors are discussed in this paper. Different routes for stress implementations in Ge channels, either biaxial or uniaxial, are proposed by advanced selective Chemical Vapor Deposition techniques. Selective SiGe Strained Relaxed Buffer growth in Shallow Trench Isolation is first discussed to implement biaxial compressive strained Ge Quantum Wells on top of it. Next, innovative GeSn chemical vapor deposition technique is described in order to build either uniaxial strained Ge channel with GeSn Source/Drain stressors or compressively biaxial strained GeSn Quantum Well channels on Ge buffer layers.

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Smooth and high quality epitaxial strained Ge grown on SiGe strain relaxed buffers with 70–85% Ge

Cited by 34 publications

References 17 publications

(Invited) Epitaxial Growth of Low Defect SiGe Buffer Layers for Integration of New Materials on 300 mm Silicon Wafers

(Invited) Epitaxial Growth of Low Defect SiGe Buffer Layers for Integration of New Materials on 300 mm Silicon Wafers

Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes

Biaxial and Uniaxial Compressive Stress Implemented in Ge(Sn) pMOSFET Channels by Advanced Reduced Pressure Chemical Vapor Deposition Developments

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