Soft decision decoding of BCH codes using error magnitudes

Reid, William J.; Joiner, L.L.; Komo, J.J.

doi:10.1109/isit.1997.613227

Cited by 7 publications

(8 citation statements)

References 1 publication

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“…Nevertheless, soft BCH decoders with lower complexity can be revealed by focusing on the least reliable bits instead of the entire codeword. In 1997, a soft BCH decoding using error magnitudes to deal with the least reliable bits was developed [16]. This soft decoder collects unreliable bits for decoding.…”

Section: Anmentioning

confidence: 99%

“…4(a) shows that there is approximately 0.25 dB performance loss at BER in the additive white Gaussian noise (AWGN) channel as compared with the hard (255,239) BCH decoder, indicating that soft information from the AWGN channel is not sufficiently reliable. However, the soft BCH decoder based on [16] can provide 0.25 dB performance gain with soft information from a 16-state Bahl-Cocke-Jelinek-Raviv (BCJR) decoder [17], as shown in Fig. 4(b).…”

Section: Anmentioning

confidence: 99%

“…Based on the concept of [16], Fig. 5 shows the proposed soft BCH decoder that includes three major steps: syndrome calculator, error locator evaluator, and error magnitude solver [18].…”

Section: Proposed Soft Bch Decoding Algorithmmentioning

confidence: 99%

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A 26.9 K 314.5 Mb/s Soft (32400,32208) BCH Decoder Chip for DVB-S2 System

Lin

Chen

Chang

et al. 2010

IEEE J. Solid-State Circuits

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Abstract-This paper provides a soft Bose-Chaudhuri-Hochquenghem (BCH) decoder chip with soft information from the LDPC decoder for the DVB-S2 system. In contrast with the hard BCH decoder, the proposed soft BCH decoder that deals with least reliable bits can provide much lower complexity with similar error-correcting performance. Moreover, the error locator evaluator is proposed to evaluate error locations without the Chien search for higher throughput, and the Björck-Pereyra error magnitude solver (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The chip measurement results reveal that our proposed soft (32400, 32208) BCH decoder for DVB-S2 system can achieve 314.5 Mb/s with a gate-count of 26.9 K in standard 90 nm 1P9M CMOS technology. Extended for fully supporting 21 modes in the DVB-S2 system, our approach can achieve 300 MHz operation frequency with a gate-count of 32.4 K.

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Section: Anmentioning

confidence: 99%

Section: Anmentioning

confidence: 99%

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A 26.9 K 314.5 Mb/s Soft (32400,32208) BCH Decoder Chip for DVB-S2 System

Lin

Chen

Chang

et al. 2010

IEEE J. Solid-State Circuits

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“…Nevertheless, soft BCH decoders with lower complexity can be revealed by focusing on the least reliable bits instead of the whole codeword. A soft BCH decoding algorithm using error magnitudes to deal with the least reliable bits was developed in 1997 [8]. However, Fig.…”

Section: Introductionmentioning

confidence: 99%

“…For the existing soft decision algorithms, the soft BCH decoder provides either better error correcting performance or lower hardware complexity than a traditional hard BCH decoder. In this paper, a soft BCH decoder which has similar concept as [8] and enhances the correcting performance by compensating one extra error while maintaining the low hardware complexity is presented. The conventional BCH decoding contains three major steps : syndrome calculator, key equation solver, and Chien search.…”

Section: Introductionmentioning

confidence: 99%

An improved soft BCH decoder with one extra error compensation

Lin

Chang

Lee

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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Abstract-In existing soft decision algorithms, a soft BCH decoders provides better error correcting performance but has much higher hardware complexity than a traditional hard BCH decoder. In this paper, a soft BCH decoder with both better error correcting performance and lower complexity is presented. The low complexity feature of the proposed architecture is achieved by dealing with least reliable bits. By compensating extra one error outside the least reliable set, the error correcting ability is improved. In addition, the proposed error locator evaluator evaluates error locations without Chien search, leading to high throughput. As compared with the traditional hard BCH decoder, the experimental result reveals that our proposed improved soft BCH decoder can achieve 0.75db coding gain for BCH (255,239) code. Implemented in standard CMOS 90nm technology, it can reach 316.3Mb/s throughput at 360MHz operation frequency with gate-count of 4.06K according to the post-layout simulations.

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