Soft-edge flip-flops for improved timing yield: design and optimization

Joshi,; Blaauw,; Sylvester,

doi:10.1109/iccad.2007.4397342

Cited by 28 publications

(20 citation statements)

References 7 publications

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“…The proposed solution works in a conservative manner that guarantees "always correct" computation and timing correctness of the circuit with respect to the delayed clock edge, even in the worst-case scenario. [26], Blueshift [27] Razor [12], DSTB, TDTB [14], TIMBER [17], soft edge flip-flop [16] SlackOptimizer, SkewOptimizer, CombOpt [29] Retiming [21], skew scheduling [23], gate sizing [24] Proposed SBFF + logic downsizing [27] Razor [12], DSTB, TDTB [14], TIMBER [17], soft edge flip-flop [16] SlackOptimizer, SkewOptimizer, CombOpt [29] Retiming [21], skew scheduling [23], gate sizing [24] Proposed SBFF + logic downsizing The proposed approach, which is an extension of our previous work [35], leverages the underutilized slack present in processor pipelines after the tool-based optimizations. We use Static Timing Analysis (STA) to look for near critical endpoints with sufficient consecutive slack after placement and logic optimizations.…”

Section: Razor Slack Reclaimedmentioning

confidence: 99%

Opportunistic Design Margining for Area and Power Efficient Processor Pipelines in Real Time Applications

Jayakrishnan

Chang²,

Kim

2018

JLPEA

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Abstract:The semiconductor industry is strategically focusing on automotive markets, and significant investment is targeted to addressing these markets. Runtime better-than-worst-case designs like Razor lead to massive timing errors upon breaching the critical operating point and have significant area overheads. As we scale to higher-reliability automotive and industrial markets we need alternative techniques that will allow full extraction of the power benefits without sacrificing reliability. The proposed method utilizes positive slack available in the pipeline stages and re-distributes it to the preceding critical logic stage using Slack Balancing Flip-Flops (SBFFs). We use opportunistic under designing to get rid of the area, power and error correction overheads associated with the speculative hardware of runtime techniques. The proposed logic reshaping results in 12 percent and eight percent power and area savings respectively compared to the worst-case design approach. Compared to runtime better-than-worst-case designs, we get 51 percent and 10 percent power and area savings, respectively. In addition, the timing budgeting and timing correction using opportunistic slack eliminate critical operating point behavior, metastability issues and hold buffer overheads encountered in existing runtime resilience techniques.

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Section: Razor Slack Reclaimedmentioning

confidence: 99%

Opportunistic Design Margining for Area and Power Efficient Processor Pipelines in Real Time Applications

Jayakrishnan

Chang²,

Kim

2018

JLPEA

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“…For example according to [17], a 40°C junction temperature rise results in a logic and wire delay increase of roughly 5% in a 130-nm industrial process. The variation of critical path delay of a logic block may be modeled by a probability distribution function (PDF) such as a Gaussian (Normal) distribution [15] with some mean, μ , and some standard deviation,σ , as is done in [8]. Accounting for the variability of path delays in Equations (1)- (2) leads to a probability of violating the setup or hold conditions.…”

Section: Preliminariesmentioning

confidence: 99%

“…Soft-edge flip-flops have been traditionally used for minimizing the effect of clock skew on static and dynamic circuits [6,7]. Recently, the authors of [8] proposed an interesting approach to utilize soft-edge flip-flops in sequential circuits in order to minimize the effect of process variation on the yield. They formulated the problem of statistically aware SEFF assignment which maximizes the gain in timing yield as an integer linear program (ILP) and proposed a heuristic algorithm to solve the problem.…”

Section: Introductionmentioning

confidence: 99%

Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing

Ghasemazar

Pedram

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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“…However, the DLs mentioned above consume extra amount of energy. Authors in [9] [12] showed that the larger transparency window size (also known as softness) is, the more energy overhead it brings. Applying soft-edge flip-flops (SEFFs) is a useful technique to combat the process variation and improve the operating frequency.…”

Section: Introductionmentioning

confidence: 99%

“…Applying soft-edge flip-flops (SEFFs) is a useful technique to combat the process variation and improve the operating frequency. The authors of [12] proposed to utilize softedge flip-flops in sequential circuits to improve the yield in the presence of process variation. In [9], the authors proposed an SEFF-based pipeline design methodology jointly considering the voltage scaling and time borrowing, and demonstrated noticeable reduction in the energy-delay product (EDP) in the ST regime.…”

Section: Introductionmentioning

confidence: 99%

Variability-aware design of energy-delay optimal linear pipelines operating in the near-threshold regime and above

Xie

Wang

Pedram

2013

Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI

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Soft-edge flip-flop based pipelines can improve the performance and energy efficiency of circuits operating in the super-threshold (supply voltage) regime by allowing opportunistic time borrowing. The application of this technique to nearthreshold regime of operation, however, faces a significant challenge due to large circuit parameter variations that result from manufacturing process imperfections and substrate temperature changes. This paper thus addresses the issue of variability-aware design of energy-delay optimal linear pipelines that are aimed at operating in both the near-threshold and super-threshold regimes. Precisely, this goal is achieved by deriving optimal delay line configuration included in the soft-edge flip-flop design for the near-threshold and the super-threshold operations. The key is to ensure that the same transistor sizes result in effective operation of the delay line (and hence appropriate setting of the transparency window size) in both regimes of operation under process induced variations. Experimental results demonstrate the efficacy of the proposed solution.

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Soft-edge flip-flops for improved timing yield: design and optimization

Cited by 28 publications

References 7 publications

Opportunistic Design Margining for Area and Power Efficient Processor Pipelines in Real Time Applications

Opportunistic Design Margining for Area and Power Efficient Processor Pipelines in Real Time Applications

Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing

Variability-aware design of energy-delay optimal linear pipelines operating in the near-threshold regime and above

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