Soft-error Monte Carlo modeling program, SEMM

Murley, P. C.; Srinivasan, G. R.

doi:10.1147/rd.401.0109

Cited by 104 publications

(57 citation statements)

References 14 publications

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“…The modeling part should provide a model that calculates the SER for the conditions in which measured data is not available. Physical models capturing the underlying mechanisms leading to SEUs are especially useful because they allow the results to be extrapolated to future technologies [65], [66], [67], [68], [69], [70]. Fig.…”

Section: Methodsmentioning

confidence: 99%

Characterization of soft errors caused by single event upsets in CMOS processes

Karnik

Hazucha

2004

IEEE Trans.Dependable and Secure Comput.

447

211

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Abstract-Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in highperformance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

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Section: Methodsmentioning

confidence: 99%

Characterization of soft errors caused by single event upsets in CMOS processes

Karnik

Hazucha

2004

IEEE Trans.Dependable and Secure Comput.

447

211

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“…The current sources are modeled as triangular model for simplicity [14,18,20,27]. Without loss of generality, the energy particle injection occurs during very small time periods (less than ps).…”

Section: Various Peak Current I Peak Impact On V Highmentioning

confidence: 99%

“…Many previous works have proposed methods to analyze transient errors induced by radiation [14,18,20,27]. Basically, these methods have used a simulated pulse to emulate the spike induced by SEUs to simulate the effect at transistor/gate level as shown in Figure 1(b).…”

Section: Introductionmentioning

confidence: 99%

SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture

Kim

Guthaus

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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Abstract. Electric devices should be resilient because reliability issues are increasingly problematic as technology scales down and the supply voltage is lowered. Specifically, the Soft-Error Rate (SER) increases due to the reduced feature size and the reduced charge. This paper describes an adaptive method to lower memory power using a dual V dd in a column-based V dd memory with Built-In Current Sensors (BICS). Using our method, we reduce the memory power by about 40% and increase the error immunity of the memory without the significant power overhead as in previous methods.

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“…The Q crit not only depends on the collected charge but also on the shape of the current pulse. The current pulse is represented by an equivalent current source between the drain and the substrate of the transistor [14], [15], [16], [17].…”

Section: Introductionmentioning

confidence: 99%

A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA

Gill

Papachristou

Wolff

2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Soft errors in semiconductor memories occur due to charged particle strikes at the cell nodes. In this paper, we present a new asymmetric memory cell to increase the soft error tolerance of SRAM. At the same time, this cell can be used at the reduced supply voltage to decrease the leakage power without significantly increasing the soft error rate of SRAM. A major use of this cell is in the configuration memory of FPGA. The cell is designed using a 70nm process technology and verified using Spice simulations. Soft error tolerance results are presented and compared with standard SRAM cell and an existing increased soft error tolerance cell. Simulation results show that our cell has lowest soft error rate at the various supply voltages.

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Soft-error Monte Carlo modeling program, SEMM

Cited by 104 publications

References 14 publications

Characterization of soft errors caused by single event upsets in CMOS processes

Characterization of soft errors caused by single event upsets in CMOS processes

SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture

A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA

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