Soft error rate mitigation techniques for modern microcircuits

Mavis, D.G.; Eaton, P.H.

doi:10.1109/relphy.2002.996639

Cited by 279 publications

(132 citation statements)

References 8 publications

Supporting

Mentioning

131

Contrasting

Order By: Relevance

“…At higher frequencies, or for advanced technologies, the error rates for combinational logic have started to dominate [2 -5]. This can be easily explained by the lower charge requirements to represent a logic HIGH state (resulting in higher number of SETs) and the increased number of clock edges for latching SETs [3]. Recent work suggests that for 0.25 µm and smaller technologies, SETs in combinational logic will dominate single-event related reliability issues [6].…”

Section: Introductionmentioning

confidence: 99%

On-Chip Characterization of Single-Event Transient Pulsewidths

Narasimham

Ramachandran

Bhuva

et al. 2006

IEEE Trans. Device Mater. Relib.

132

View full text Add to dashboard Cite

Abstract-A new on-chip Single Event Transient (SET) test structure has been developed that can autonomously measure the width of random SET pulses. Simulation results show measurement granularity of 900 ps for a 1.5 µm technology and 65 ps for 0.13 µm technology. Laser tests were used to obtain experimental data on test chips fabricated using 1.5 µm process. Experimental measurements show pulse widths varying from 900 ps to over 3 ns as the laser energy is increased.Index Terms-Single event transient (SET), transient pulse width

show abstract

Section: Introductionmentioning

confidence: 99%

On-Chip Characterization of Single-Event Transient Pulsewidths

Narasimham

Ramachandran

Bhuva

et al. 2006

IEEE Trans. Device Mater. Relib.

132

View full text Add to dashboard Cite

show abstract

“…This failure risk increases with process scaling, and therefore, many alternative SRAM circuits have been proposed in recent years. Recently proposed rad-hard designs include the temporal latch [18], DICE [19], the Quatro-10T and 12T bitcells [21], [22], the 13T subthreshold bitcell [20], and SHIELD [23]. These solutions can be fabricated in commercially available state-of-the-art manufacturing processes at the expense of an increase in the silicon area of the bitcell.…”

Section: Circuit Level Solutionsmentioning

confidence: 99%

Single event upset mitigation in low power SRAM design

Atias

Teman

Fish

2014

2014 IEEE 28th Convention of Electrical &Amp; Electronics Engineers in Israel (IEEEI)

View full text Add to dashboard Cite

Abstract-Technology advancements in recent years have led to an increase in the employment of integrated circuits in space applications. However, these applications operate in a highly radiated environment, causing a high probability of single event upsets (SEU). Continuous transistor scaling exacerbates the situation, as susceptibility to SEUs is increased in advanced process technologies. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Accordingly, maintaining data integrity in light of SEUs has become an integral aspect of memory cell design. This paper introduces recently proposed methods for mitigating SEUs, and reviews the advantages and disadvantages of leading memory radiation hardening solutions. A brief comparison of radiation hardened bitcells is provided, based on Monte Carlo simulations in a 65 nm CMOS process under slightly scaled supply voltages.

show abstract

“…2(b)) with an interval greater than the pulse width of the SET. Then it stores the sampled values in different latches and uses majority voting to determine the correct data [6]. This technique can detect and correct a SEU for an SET on the data line.…”

Section: Seu Hardening Techniques For Flip-flopsmentioning

confidence: 99%