Soft Error Sensitivity Analysis Based on 40 nm SRAM-Based FPGA

Xu, Xiong; Du, Xuecheng; Zheng, B.; Chen, Zhi; Jiang, Wei; He, Sanjun; Zhu, Yixin

doi:10.3390/electronics11233844

Cited by 3 publications

(3 citation statements)

References 22 publications

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“…To mitigate soft errors in integrated circuits for space applications, it is crucial to evaluate the soft error rate (SER) during the circuit design phase. In previous works, several circuit-level evaluation approaches have been proposed to investigate the SER of integrated circuits [11][12][13][14][15][16][17][18][19][20][21]. These works have proposed many accurate models to generate transient pulses in circuit nodes.…”

Section: Introductionmentioning

confidence: 99%

Machine Learning-Based Soft-Error-Rate Evaluation for Large-Scale Integrated Circuits

Song,

Shao,

Chi

et al. 2023

Electronics

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Transient pulses generated by high-energy particles can cause soft errors in circuits, resulting in spacecraft malfunctions and posing serious threats to the normal operation of spacecraft. For integrated circuits used in space applications, it is necessary to first evaluate soft errors caused by transient pulses. Conventional soft-error-rate evaluation tools are designed to simulate the generation of transient pulses using many accurate models, while the propagation of transient pulses is primarily simulated by circuit-level simulation tools. Due to the limitations of simulation tools, conventional evaluation approaches are limited to the circuit scale. The simulation runtime is unbearable for large-scale integrated circuits. This paper presents an approach for evaluating the soft error rate using machine learning. A back propagation neural network is implemented in the proposed approach. It helps to determine the probability of transient pulse propagation. Compared with the conventional soft-error-rate evaluation results, the proposed approach demonstrates a strong correlation in both trend and magnitude. The average difference between the results obtained using the proposed evaluation method and the experimental results is 23.5%, which is 7.5% higher than that between the results obtained using the conventional evaluation method and the experimental results. Compared to the conventional evaluation method, the proposed approach improves the runtime by an order of magnitude. The proposed approach also benefits the locating of highly sensitive circuit nodes in large-scale integrated circuits. Circuit design and radiation hardening are both useful applications.

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Section: Introductionmentioning

confidence: 99%

Machine Learning-Based Soft-Error-Rate Evaluation for Large-Scale Integrated Circuits

Song,

Shao,

Chi

et al. 2023

Electronics

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“…This flaws could cause the CPU to improperly execute a programme, causing SDC or system delays and failures. Soft mistakes in FPGAs can affect the setup stream of bits, causing changes in the device's logic, function, and effectiveness [1,2]. SRAM-dependent Field-Programmable Gate arrays are used in high-performance processors with dual-core ARM Cortex-A9 processors like the Xilinx Zynq-7000 and Altera Cyclone-V. (FPGAs).…”

Section: Introductionmentioning

confidence: 99%

Dependability Measurement with Soft Error Caused Exceptions on the Arm Cortex-A9 CPU

Mahmood

2023

Int j comput electron asp eng

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In embedded systems, ARM processors are the market leaders, offering highperformance computation, low power consumption, and low cost. As a result, there is a lot of excitement about its potential in the aerospace business. The Xilinx Zynq-7000 FPGA features dualcore ARM Cortex-A9 hard-core processors. are protected from soft failures thanks to a lockstep technique described in this study. The lockstep is an error detection and righting system that is based on both hardware and software. At the software level, it uses checkpoints and rollback methods. On the hardware level, checker circuits and processor replication are also included. The proposed method demonstrates how to execute the plan successfully in two core processors to improve system stability in radiation environments. The results reveal a link between the size of the application and the checkpoint and rollback strategies in terms of usability overhead. as well as a dependence on the number of checkpoints.

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“…Within Synchronous Dynamic Random-Access Memory (SDRAM), the logical state of mode register flip-flops can induce SEFI, while flip-flops in the READ latch region can also contribute to SEFI, which can be rectified through software or power cycling [9,10]. Configuration Random-Access Memory (CRAM) storage units in Static Random-Access Memory (SRAM)-based Field Programmable Gate Arrays (FPGAs) are employed for user logic implementation, and the occurrence of a flip-flop anomaly in this area may lead to abnormal FPGA functionality with a certain probability [11][12][13]. Similarly, ADC devices encompass internal control registers or circuits, and high-energy particle impacts in these regions can trigger SEFI in ADCs, posing a significant threat to their reliability [14].…”

Section: Introductionmentioning

confidence: 99%

Experiment Study of Single Event Functional Interrupt in Analog-to-Digital Converters Using a Pulsed Laser

Mai

Zhu

et al. 2023

Electronics

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Single Event Functional Interrupt (SEFI) poses a severe threat to the normal operation of spacecraft. This paper investigates SEFI in Analog-to-Digital Converters (ADCs) with storage units using precision positioning of pulsed lasers. Based on the experiment, it was discovered that a bit flip in the configuration registers in ADCs results in changes in parameters such as digital filter frequency, operating mode, and gain, leading to an upward or downward offset of ADC output codes. Similarly, a bit flip in the calibration registers also causes ADC output codes to shift upwards or downwards, or even output a value of zero. Furthermore, it was observed that SEFI phenomena can occur due to current latch-up in ADC input pins, causing the inability to read or write data in ADC storage units. This current latch-up can be resolved through power cycling or configuring the pins into a high-impedance state. This work highlights the significance of SEFI phenomena in ADCs, emphasizing the serious threat posed by storage unit flipping-induced SEFI to the proper functioning of ADCs. Moreover, the SEFI phenomenon caused by current latch-up in input pins is difficult to detect in practice, making it highly elusive. Once it occurs, it severely impacts the functionality of ADCs.

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Soft Error Sensitivity Analysis Based on 40 nm SRAM-Based FPGA

Cited by 3 publications

References 22 publications

Machine Learning-Based Soft-Error-Rate Evaluation for Large-Scale Integrated Circuits

Machine Learning-Based Soft-Error-Rate Evaluation for Large-Scale Integrated Circuits

Dependability Measurement with Soft Error Caused Exceptions on the Arm Cortex-A9 CPU

Experiment Study of Single Event Functional Interrupt in Analog-to-Digital Converters Using a Pulsed Laser

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