Software pipelining

Allan, Vicki H.; Jones, Reese B.; Lee, Randall M.; Allan, Stephen J.

doi:10.1145/212094.212131

Cited by 276 publications

(102 citation statements)

References 21 publications

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“…However, we lack of interesting scheduling techniques, e.g. software pipelining [2], which are quite profitable considering the underlying architecture and our application domain.…”

Section: Related and Future Workmentioning

confidence: 99%

“…when addressing data registers. Given the Directed Acyclic Graph (DAG) G = (I, E) of data-dependent instructions, where I is the set of instructions, it walks G starting from a random load or store i0, save its address 2 In particular the Length Strength Reduce (LSR) optimization pass space number and look if it finds a cross address space usage at some other data-related load or store in. The data path P = (i1, in−1) → P ′ is then cloned and in, the faulty memory access, is modified to use i ′ n−1 as its new operand.…”

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confidence: 99%

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Code generation for an application-specific VLIW processor with clustered, addressable register files

Llopard

Cohen

Fabre

et al. 2013

Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems

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Modern compilers integrate recent advances in compiler construction, intermediate representations, algorithms and programming language front-ends. Yet code generation for application-specific architectures benefits only marginally from this trend, as most of the effort is oriented towards popular general-purpose architectures. Historically, non-orthogonal architectures have relied on custom compiler technologies, some retargettable, but largely decoupled from the evolution of mainstream tool flows.Very Long Instruction Word (VLIW) architectures have introduced a variety of interesting problems such as clusterization, packetization or bundling, instruction scheduling for exposed pipelines, long delay slots, software pipelining, etc. These have been addressed in the literature, with a focus on the exploitation of Instruction Level Parallelism (ILP). While these are well known solutions already embedded into existing compilers, they rely on common hardware functionalities that are expected to be present in a fairly large subset of VLIW architectures.This paper presents our work on back-end compiler for Mephisto, a high performance low-power application-specific processor, based on LLVM. Mephisto is specialized enough to challenge established code generation solutions for VLIW and DSP processors, calling for an innovative compilation flow. Conversely, even though Mephisto might be seen a somewhat exotic processor, its hardware characteristics such as addressable register files benefit from existing analyses and transformations in LLVM. We describe our model of the Mephisto architecture, the difficulties we encountered, and the associated compilation methods, some of them new and specific to Mephisto.

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“…However, we lack of interesting scheduling techniques, e.g. software pipelining [2], which are quite profitable considering the underlying architecture and our application domain.…”

Section: Related and Future Workmentioning

confidence: 99%

mentioning

confidence: 99%

Code generation for an application-specific VLIW processor with clustered, addressable register files

Llopard

Cohen

Fabre

et al. 2013

Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems

View full text Add to dashboard Cite

show abstract

“…An extensive survey of the available software pipelining techniques such as modulo scheduling algorithms, perfect pipelining, Petri net model and Vegdahl's technique, and a comparison between the different methods is given in [17]. Since basic-block scheduling is an NP-hard problem [18], most effort on the topic has been focused on a variety of heuristics to reach nearoptimal schedules.…”

Section: Chapter 7 Related Workmentioning

confidence: 99%

Efficient pipelining of nested loops: unroll-and-squash

Petkov

Harr²,

Amarasinghe³

2002

Proceedings 16th International Parallel and Distributed Processing Symposium

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The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology to map abstract designs into silicon. Many applications operating on large streaming data usually require a custom VLSI because of high performance or low power restrictions. Since the data processing is typically described by loop constructs in a high-level language, loops are the most critical portions of the hardware description and special techniques are developed to optimally synthesize them. In this thesis, we introduce a new method for mapping nested loops into hardware and pipelining them efficiently. The technique achieves fine-grain parallelism even on strong intra-and inter-iteration datadependent inner loops and, by economically sharing resources, improves performance at the expense of a small amount of additional area. We implemented the transformation within the Nimble Compiler environment and evaluated its performance on several signal-processing benchmarks. The method achieves up to 2x increase in the area efficiency compared to the best known optimization techniques.

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“…Software pipelining [1,2,4,6,7,10,13,14,15,16] is a well known compilation technique that improves the performance of a loop by overlapping the execution of independent instructions from several iterations. The execution of a softwarepipelined loop goes through three phases: prolog, when the pipeline is filled -i.e.…”

Section: Introductionmentioning

confidence: 99%

Software Pipelining of Nested Loops

Muthukumar

Doshi

2001

Lecture Notes in Computer Science

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Abstract. Software pipelining is a technique to improve the performance of a loop by overlapping the execution of several iterations. The execution of a software-pipelined loop goes through three phases: prolog, kernel, and epilog. Software pipelining works best if most of the time is spent in the kernel phase rather than in the prolog or epilog phases. This can happen only if the trip count of a pipelined loop is large enough to amortize the overhead of prolog and epilog phases. When a softwarepipelined loop is part of a loop nest, the overhead of filling and draining the pipeline is incurred for every iteration of the outer loop. This paper introduces two novel methods to minimize the overhead of softwarepipeline fill/drain in nested loops. In effect, these methods overlap the draining of the software pipeline corresponding to one outer loop iteration with the filling of the software pipeline corresponding to one or more subsequent outer loop iterations. This results in better instructionlevel parallelism (ILP) for the loop nest, particularly for loop nests in which the trip counts of inner loops are small. These methods exploit Itanium T M architecture software pipelining features such as predication, register rotation, and explicit epilog stage control, to minimize the code size overhead associated with such a transformation. However, the key idea behind these methods is applicable to other architectures as well. These methods have been prototyped in the Intel optimizing compiler for the Itanium T M processor. Experimental results on SPEC2000 benchmark programs are presented.

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Software pipelining

Cited by 276 publications

References 21 publications

Code generation for an application-specific VLIW processor with clustered, addressable register files

Code generation for an application-specific VLIW processor with clustered, addressable register files

Efficient pipelining of nested loops: unroll-and-squash

Software Pipelining of Nested Loops

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