SOI LDMOS With High-k Multi-Fingers to Modulate the Electric Field Distributions

Yao, Jiafei; Sun, Mingshun; Xu, Tianci; Liu, Xin; Li, Man; Chen, Jing; Zhang, Maolin; Zhang, Jun; Guo, Yufeng

doi:10.1109/ted.2023.3262224

Cited by 8 publications

(4 citation statements)

References 16 publications

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“…Silicon on insulator (SOI) lateral double‐diffused metal oxide semiconductor (LDMOS) typically operates in harsh environments with high voltage. Conventionally, to increase the breakdown voltage (BV) of SOI LDMOS, various techniques have been proposed [1–6]. Among these techniques, the field plate (FP) technology has gained widespread popularity due to its simplified fabrication process and superior capability in improving performance.…”

Section: Introductionmentioning

confidence: 99%

Automatic optimal design of field plate for silicon on insulator lateral double‐diffused metal oxide semiconductor using simulated annealing algorithm

Chen,

Xia,

You

et al. 2024

IET Power Electronics

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Field plate (FP) technology has been widely used due to its simple structure and process compatibility. Through introducing the interface charge to suppress the electric field peak at the junction region, the breakdown performance can be improved. However, designing an appropriate FP for semiconductor power devices is challenging and time‐consuming. In this paper, the authors propose a fully automated FP optimal design method based on simulated annealing algorithm (SA) for silicon on insulator lateral double‐diffused metal oxide semiconductor. By using an automatic iterative process to obtain the minimum value of the objective function, the parameters related to the FP can be effectively provided. Numerical results show that when the breakdown occurs at the N+N or PN junction, the breakdown voltage can be optimized by an average of 18.6% and 45.5%, respectively. Moreover, compared with the existing methods, the proposed approach is highly efficient with a runtime that does not exceed 12 s. The authors believe that this method can greatly accelerate the power device design process.

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Section: Introductionmentioning

confidence: 99%

Automatic optimal design of field plate for silicon on insulator lateral double‐diffused metal oxide semiconductor using simulated annealing algorithm

Chen,

Xia,

You

et al. 2024

IET Power Electronics

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“…The introduction of Low-k (LK) dielectric material is intended to increase the vertical BV of the device through the application of enhanced dielectric layer field technology. Therefore, scholars have done a lot of research in this direction in recent years [9][10][11][12][13][14]. Cheng et al [9] introduced a HK thin film around the trench, the BV and R on,sp of LDMOS were effectively improved.…”

Section: Introductionmentioning

confidence: 99%

“…Cheng et al [9] introduced a HK thin film around the trench, the BV and R on,sp of LDMOS were effectively improved. Moreover [10], proposed a LDMOS with HK multi-fingers, and the doping concentration is increased due to the drift region of HK dielectric. Yao et al [14] investigated a double dielectrics enhancement LDMOS with a HK field dielectric and a LK buried layer dielectric.…”

Section: Introductionmentioning

confidence: 99%

A novel double-gate trench SOI LDMOS with double-dielectric material by TCAD simulation study

Guo,

Dai,

Wang

et al. 2024

Semicond. Sci. Technol.

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In this paper, a novel double-gate trench silicon-on-insulator (SOI) lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with double-dielectric material (DGDK-LDMOS) is proposed. DGDK-LDMOS has two dielectric materials: a reverse-L-shaped high-k (HK) thin film and an low-k (LK) buried oxide layer. The HK thin film optimizes the electric field distribution on the drift region surface, attracting electric flux, and the excellent withstand voltage of the LK buried oxide layer can significantly improve the breakdown voltage (BV) and reduce specific on-resistance (Ron,sp) of the device. The modulation mechanism of LDMOS by HK thin film and LK buried oxide layer is analyzed. The results show that compared with conventional LDMOS (C-LDMOS), when the permittivity of HK thin film is 25 and the permittivity of LK buried oxide is 3, the BV of DGDK-LDMOS is increased by 89.6%, the Ron,sp is decreased by 26.4%, and the figure of merit (FOM, FOM = BV2/Ron,sp) is increased by 397.2% from 3.6 MW·cm−2 to 17.9 MW·cm−2. Meanwhile, the output characteristics, transfer characteristics, lattice temperature, AC characteristics and switching characteristics of DGDK-LDMOS are also discussed and compared.

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“…Laterally diffused metal oxide semiconductor (LDMOS) devices have been widely adopted in power integrated circuits due to its high Breakdown Voltage (BV) and low speci c on-resistance (R onsp ) [1][2][3][4][5]. It is the key determinant of the performance, cost, and integration level of power integrated circuits [6,7].…”

Section: Introductionmentioning

confidence: 99%

An Ultra-Fast and Precise Automatic Design Framework for Predicting and Constructing High-Performance Shallow-Trench-Isolation LDMOS Device

Xu,

Tang,

Zhu

et al. 2024

Preprint

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Shallow Trench Isolation laterally diffused metal oxide semiconductor (STI LDMOS) is a crucial device for power integrated circuits. In this article, a novel framework that integrates an optimal objective function, Bayesian Optimization (BO) algorithm and Deep Neural Network (DNN) model is proposed to fully realize automatic and optimal design of STI LDMOS devices. On the one hand, given the structure of device, the DNN model in the proposed method can provide the ultra-fast and high-accurate performance estimation including breakdown voltage (BV) and specific on-resistance (Ronsp). The experimental results demonstrate 98.68% prediction accuracy in average for both BV and Ronsp, higher than that of other machine learning (ML) algorithms. On the other hand, to target the specified value of BV and Ronsp, the proposed framework can fully automatically and optimally design the precise device structure that simultaneously achieves the target performance with the optimal figure-of-merit (FOM) of device. Compared to Technology Computer Aided Design (TCAD), there is only 0.002% error in FOM and 2.83% average error in BV and Ronsp. Moreover, the proposed framework is 4000 times more efficient than other conventional frameworks. Thus, this research provides experimental groundwork for constructing an automatic design framework for LDMOS device and opens up new opportunities for accelerating the development of LDMOS device in the future.

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SOI LDMOS With High-k Multi-Fingers to Modulate the Electric Field Distributions

Cited by 8 publications

References 16 publications

Automatic optimal design of field plate for silicon on insulator lateral double‐diffused metal oxide semiconductor using simulated annealing algorithm

Automatic optimal design of field plate for silicon on insulator lateral double‐diffused metal oxide semiconductor using simulated annealing algorithm

A novel double-gate trench SOI LDMOS with double-dielectric material by TCAD simulation study

An Ultra-Fast and Precise Automatic Design Framework for Predicting and Constructing High-Performance Shallow-Trench-Isolation LDMOS Device

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