Some Device Design Considerations to Enhance the Performance of DG-MOSFETs

Abstract

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current (I off ), on current (I on ), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

3-D Simulation of Nanoscale SOI n-FinFET at a Gate Length of 8 nm Using ATLAS SILVACO

“…Furthermore, SS is calculated as in [4,5]: (6) A typical value for the SS parameter of a MuGFET is 60 mV /decade, (i.e., a 60 mV change in gate voltage brings about a tenfold change in drain current) [4,5]. The subthreshold slope is 69.13 mV/decade in the considered n-FinFET device at V DS = 0.1 V.…”

“…Fig. 4 shows, that the leakage current output I off is 17.3 pA at V GS = 0 V and V DS = 0.9 V. I off has been calculated by the following formula in [4,5]: (7) The leakage current and on-current of the considered device (i.e., 17.3 pA and 33.26 μA) are improved compared with the results of the recent paper reporting on a 16 nm n-type FinFET (i.e., 164 pA and 31.6 μA) [6]. The lowering of I off is a valuable result in order to minimize the static power dissipation even when the device is in the standby mode.…”

“…The transconductance g m quantifies the drain current variation with a gate-source voltage variation while keeping the drainsource voltage constant [4,5]:…”

“…4, it is observed that the on-state current output is 33.26 μA at V GS = V DS = V DD and V DS = 0.9 V, where V DD is the supply voltage. Furthermore, I DS is calculated as reported in [4,5]:…”

“…The value of the drain induced barrier lowering (DIBL) is calculated by using the relation reported in [4,5]:…”