SON (silicon on nothing)-a new device architecture for the ULSI era

Jurczak, M.; Skotnicki, T.; Paoli, M.; Tormen, B.; Régolini, J. L.; Morin, Christine; Schiltz, A.; Martins, Jorge; Pantel, R.; Galvier, J.

doi:10.1109/vlsit.1999.799324

Cited by 32 publications

(9 citation statements)

References 3 publications

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“…To overcome the problems mentioned above, there were several efforts [6]- [11]. In this letter, we propose and fabricate new structure MOSFETs for the first time with conventional CMOS process, partially insulated field effect transistors (PiFETs), partially insulating oxide (PiOX) under source/drain (S/D) (PUSD) and PiOX under channel (PUC), on bulk silicon.…”

Section: Introductionmentioning

confidence: 99%

A Partially Insulated Field-Effect Transistor (PiFET) as a Candidate for Scaled Transistors

Yeo

Kim

et al. 2004

IEEE Electron Device Lett.

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Highly manufacturable partially insulated field-effect transistors (PiFETs) were fabricated by using Si-SiGe epitaxial growth and selective SiGe etch process. Owing to these technologies, pseudo-silicon-on-insulator (SOI) structures, partially insulating oxide (PiOX) under source/drain (PUSD) and PiOX under channel (PUC), could be easily realized with excellent structural and process advantages. We are demonstrating their preliminary characteristics and properties. Especially, in the PUSD PiFET, junction capacitance, leakage current, and DIBL in bulk devices could be reduced and the floating body problem in SOI devices was also cleared without any area penalty. Thus, this PiFET structure can be a promising candidate for the future DRAM cell transistor. Index Terms-Epitaxial growth, partially insulated field-effect transistors (PiFETs), partially insulating oxide (PiOX), PiOX under channel (PUC), PiOX under source/drain (PUSD), SiGe.

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Section: Introductionmentioning

confidence: 99%

A Partially Insulated Field-Effect Transistor (PiFET) as a Candidate for Scaled Transistors

Yeo

Kim

et al. 2004

IEEE Electron Device Lett.

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“…2) were added to our former SONbased [6] process fabrication scheme [4] without an additional lithography step. They are introduced after the Si/SiGe superlattice epitaxy and anisotropic etching.…”

Section: Process Descriptionmentioning

confidence: 99%

First Internal Spacers' Introduction in Record High $I_{\rm ON}/I_{\rm OFF}\ \hbox{TiN/HfO}_{2}$ Gate Multichannel MOSFET Satisfying Both High-Performance and Low Standby Power Requirements

Bernard

Ernst

Guillaumot

et al. 2009

IEEE Electron Device Lett.

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For the first time, internal spacers have been introduced in multichannel CMOSFET (MCFET) structures, featuring a decrease of the intrinsic CV /I delay by 39%. The process steps introduced for this new MCFET technological option are studied and optimized in order to achieve excellent I ON /I OFF characteristics (NMOS: 2.33 mA/μm at 27 pA/μm and PMOS: 1.52 mA/μm at 38 pA/μm). A gate capacitance C gg reduction of 32% is measured, thanks to S-parameter extraction. Moreover, a significant improvement of the analogical figure of merit is measured compared with optimized fully depleted silicon-on-insulator planar reference; the voltage gain A VI (= g m /g ds ) is improved by 92%.Index Terms-A VI , C gg , CV /I, high performances, internal spacers, low standby power, multichannel CMOSFETs (MCFETs), 3-D.

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“…Recently, an air-gap transistor, which has a void under the transistor region, has been proposed as one of the ideal structure of SOI, because the dielectric constant at the region below the transistors could be 1 with this structure. 6,7 However, the proposed process sequences were too complicated for fabrication of LSI, because the air gap was formed by the etching step after device fabrication. Thus, it is difficult to enlarge the void region.…”

Section: ͓S0003-6951͑00͒00846-9͔mentioning

confidence: 99%

Empty-space-in-silicon technique for fabricating a silicon-on-nothing structure

Mizushima

Sato

Taniguchi

et al. 2000

Applied Physics Letters

133

109

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A promising technique to form the silicon-on-nothing structure is presented as an alternative to the silicon-on-insulator structure. A large plate-shaped empty space in silicon (ESS) below the surface of the silicon substrate can be fabricated by connecting the spherical empty spaces, which are formed by surface migration of Si on the patterned Si substrate. The ESS technique has the potential to change the microprocess for the fabrication of large-scale integrated circuits and it can be applied to various manufacturing technologies.

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SON (silicon on nothing)-a new device architecture for the ULSI era

Cited by 32 publications

References 3 publications

A Partially Insulated Field-Effect Transistor (PiFET) as a Candidate for Scaled Transistors

A Partially Insulated Field-Effect Transistor (PiFET) as a Candidate for Scaled Transistors

First Internal Spacers' Introduction in Record High $I_{\rm ON}/I_{\rm OFF}\ \hbox{TiN/HfO}_{2}$ Gate Multichannel MOSFET Satisfying Both High-Performance and Low Standby Power Requirements

Empty-space-in-silicon technique for fabricating a silicon-on-nothing structure

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