SONOS Device With Tapered Bandgap Nitride Layer

Nitride engineering and the effect of interfaces on Charge Trap Flash performance and reliability

“…Though there is a strong dependence on the position of the SiON interface layer, the erase state V FB shows negligible degradation for Si + /N + = 4/4 and 6/2 (nm) bi-layer device. This is in stark contrast to the single layer nitride endurance results in this study as well as in the literature [3], [6], [7], [16], [17] and consistent with recent results on NAN stacks [8] cycling endurance is worth a mention as the improvement is inexplicable by attribution to simply the ratio of Si + vs. N + nitride layer thickness in the bi-layer stack (as plausible in the case of W/E or retention performance). The signature effect of the SiON barrier layer explains the improvement for the bi-layer endurance as single layer nitride endurance is poor -regardless of the choice of nitride composition.…”

“…1. The trap density of Si + and N + layers [11] and the band gaps [6] are indicated in accordance with the existing literature. Similar diagrams for the bi-layer nitride stacks with the interfacial SiON layer is indicated in Fig.…”

“…This band gap engineered storage node shows improved performance and reliability over single uniform nitride layer (this work) and graded-nitride devices reported elsewhere [6]. Comparable performance to the advanced NAN stack [8] is demonstrated, though with the advantage of simpler process integration by avoiding the incorporation of high-k dielectrics.…”

“…In the past, band gap engineering of the tunnel dielectric [4], [5] as well as of the silicon nitride storage layer [6], [7] has been done to improve CTF memory window and reliability. The use of multi-layer deposited tunnel dielectric [4], [5] instead of conventional thermally grown SiO 2 may compromise the overall cell reliability, especially for Multi-Level Cell (MLC) operation that requires high Write/Erase (W/E) voltages for high memory window.…”

“…Therefore, engineering the silicon nitride charge trap layer is a promising strategy to enhance the performance of CTF. Nitride composition gradients that resulted in a tapered band-gap structure demonstrated high memory window and retention but poor cycling endurance [6]. Recently, the use of silicon nitride-aluminum oxide-silicon nitride (NAN) composite as a storage layer demonstrated high memory window, good data retention and cycling endurance [8].…”