SoPC Architecture for a Key Point Detector

Chati, Harding Djakou; Mühlbauer, Felix; Braun, Torsten; Bobda, Christophe; Berns, Karsten

doi:10.1109/fpl.2007.4380751

Cited by 6 publications

(4 citation statements)

References 3 publications

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“…Another FPGA-based partial implementation of the SIFT algorithm is reported in [24,25]. A hardware-software codesign strategy was preferred over pure hardware implementation; the hardware-software partitioning was done in such a way that the detection phase of the algorithm was implemented in hardware whereas the description phase was targeted to run in software on a MicroBlaze processor.…”

Section: Hardware Based Extractionmentioning

confidence: 99%

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Hardware Based Scale- and Rotation-Invariant Feature Extraction: A Retrospective Analysis and Future Directions

Ehsan

Clark

McDonald-Maier

2009

2009 Second International Conference on Computer and Electrical Engineering

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Abstract-Computer Vision techniques represent a class of algorithms that are highly computation and data intensive in nature. Generally, performance of these algorithms in terms of execution speed on desktop computers is far from real-time. Since real-time performance is desirable in many applications, special-purpose hardware is required in most cases to achieve this goal. Scale-and rotation-invariant local feature extraction is a low level computer vision task with very high computational complexity. The state-of-the-art algorithms that currently exist in this domain, like SIFT and SURF, suffer from slow execution speeds and at best can only achieve rates of 2-3 Hz on modern desktop computers. Hardware-based scale-and rotation-invariant local feature extraction is an emerging trend enabling real-time performance for these computationally complex algorithms. This paper takes a retrospective look at the advances made so far in this field, discusses the hardware design strategies employed and results achieved, identifies current research gaps and suggests future research directions.

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Section: Hardware Based Extractionmentioning

confidence: 99%

“…With MicroBlaze running at 100 MHz, it was claimed that this architecture required 0.8 ms for detection and description of key points for an image size of 320 x 240 pixels [24]. However, according to [25], 0.8 ms is required for an image size of 340 x 240 pixels.…”

Section: Hardware Based Extractionmentioning

confidence: 99%

Hardware Based Scale- and Rotation-Invariant Feature Extraction: A Retrospective Analysis and Future Directions

Ehsan

Clark

McDonald-Maier

2009

2009 Second International Conference on Computer and Electrical Engineering

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“…There are several SIFT hardware accelerate designs proposed based on system on programmable chip (SOPC) [5,6], field-programmable gate array(FPGA) [7,8] or graphic processing unit (GPU) [9,10], and some of these approaches achieved near real-time performance improvement. These proposed hardware-based SIFT acceleration schemes can easily reach several times acceleration rate, but they often have the following disadvantages: 1) Too much power need to be consumed and thus may not very suitable for an embedded system; 2) Some important key-point detection stage is often skipped to reduce the hardware complexity, thus such simplification may sacrifice the accuracy and lead to misdetection of some features.…”

Section: Introductionmentioning

confidence: 99%

Multicore Computing for SIFT Algorithm in MATLAB® Parallel Environment

Cao

Chen

2012

2012 IEEE 18th International Conference on Parallel and Distributed Systems

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An important processing stage in computer vision such as recognizes an object is feature extraction. Among those feature extraction algorithms, Lowe proposed the scaleinvariant feature transform (SIFT) algorithm has been considered as one of the robust approaches. But due to the implementation of the convolution search operation, the computing of SIFT algorithm is highly time-consuming. There are such problems as consuming too much power, sacrifice accuracy and lacking scalability for hardware-based acceleration scheme, it is still necessary to find the softwarebased acceleration approaches, especially for some applications and researches which need high-precision matched. Matlab is a general algorithm development environment with powerful image processing and other supporting toolboxes. With the rapid development of multicore CPU technology, using multicore computer and Matlab is an intuitive and simple way to speed up the computing for SIFT algorithm. In this paper, we try to have a view for using the Matlab parallel toolbox to accelerate the SIFT algorithm by two schemes of task-parallelism and data-parallelism modal. The results show that the parallel versions of former sequential algorithm with simple modifications achieve the speedup up to 6.6 times

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“…As principais áreas de pesquisa descritas por este referencial teórico são abordadas em trabalhos recentes, alguns trabalhos de destaque serão apresentados a seguir. Chati et al (2007) apresenta um co-projeto de hardware/software para detecção de pontos chave na imagem utilizando FPGA. Este trabalho utiliza o novo paradigma de projeto devido ao aumento da complexidade dos circuitos e busca por melhores resultados.…”

Section: Trabalhos Relacionadosunclassified

Co-Projeto de hardware/software para correlação de imagens

Dias¹

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This work presents a FPGA based hardware/software co-design for image normalized cross correlation algorithm. The main goal is to achieve a significant speedup related to the execution time of the all-software implementation. The co-design proposed method is a modified profiling-based method with a software development step. The executions were compared related to execution time resulting on a significant speedup. To achieve this speedup a comparison between 21 different configurations of Nios II soft-processor was done. Also hardware influence on execution time was evaluated to know how simple hardware structures and specific hardware structures influence algorithm final execution time. Result analysis suggest that the method is very efficient considering achieved speedup but the final execution time still remains higher, considering the need for real time image processing on robotic navigation systems. However, the limitations for real time processing are a consequence of the hardware adopted in this work, based on a low cost and capacity FPGA.

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SoPC Architecture for a Key Point Detector

Cited by 6 publications

References 3 publications

Hardware Based Scale- and Rotation-Invariant Feature Extraction: A Retrospective Analysis and Future Directions

Hardware Based Scale- and Rotation-Invariant Feature Extraction: A Retrospective Analysis and Future Directions

Multicore Computing for SIFT Algorithm in MATLAB® Parallel Environment

Co-Projeto de hardware/software para correlação de imagens

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SoPC Architecture for a Key Point Detector

Cited by 6 publications

References 3 publications

Hardware Based Scale- and Rotation-Invariant Feature Extraction: A Retrospective Analysis and Future Directions

Hardware Based Scale- and Rotation-Invariant Feature Extraction: A Retrospective Analysis and Future Directions

Multicore Computing for SIFT Algorithm in MATLAB&#x00AE; Parallel Environment

Co-Projeto de hardware/software para correlação de imagens

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Multicore Computing for SIFT Algorithm in MATLAB® Parallel Environment