Sorter Based Permutation Units for Media-Enhanced Microprocessors

Dimitrakopoulos, Giorgos; Mavrokefalidis, Christos; Galanopoulos, Kostas; Nikolos, D.

doi:10.1109/tvlsi.2007.898750

Cited by 10 publications

(14 citation statements)

References 14 publications

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“…As in enhanced bi-tonic sorting network EBSN [3], the Merge Sorter Network shown in fig.1 networks called Enhanced Merge Sorters (EMS) whose purpose is analogous to the EBS unit. Also only n/2 MSB's are sufficient to guide the data rearrangement.…”

Section: Enhanced Merge Sorter Network (Ems)mentioning

confidence: 99%

“…The main strength of Enhanced Merge Sorting Network [3] lies in the control word. If even one bit of the control word is changed, the whole process and the network structure Hardware Implementation of Low Power Audio Sub word Sorter Unit for High Security Transmission changes.…”

Section: Modified Enhanced Merge Sorter Network (Mems)mentioning

confidence: 99%

“…The paper [3] expounds only the sorting technique at the transmitter side. It does not give any method to retrieve (decrypt) the data at the receiving end.…”

Section: Modified Enhanced Merge Sorter Network (Mems)mentioning

confidence: 99%

“…New structure has been designed for both the left and right data path separately. The designed structures are simpler and more efficient than the ones existing [3].…”

Section: Modified Enhanced Merge Sorter Network (Mems)mentioning

confidence: 99%

“…Separate structures have been designed for this. This has not been mentioned in [3]. Since no paper is appeared earlier related to FPGA implementation of audio sorter, we have written the code for [3] which deals only with encryption and its corresponding synthesis report converted into transistor level netlist and is implemented in Tanner EDA Tool and the power is calculated.…”

Section: Levelmentioning

confidence: 99%

See 4 more Smart Citations

Hardware Implementation of Low Power Audio Sub word Sorter Unit for High SecurityTransmission

Karthigaikumar¹,

Baskaran²

2009

IJCEE

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Abstract-The security of audio data in high end communication applications like satellites and radars is an issue of concern these days. Designing a processor at the chip level for this requirement is by itself a challenge to VLSI engineers. This paper aims to design a HDL based novel audio subword sorter unit, which is less complex in structure and highly efficient in terms of security. In this paper, we examine the hardware implementation of powerful permutation instruction group (GRP) in low power. This is done at the integrated chip (IC-level) using Verilog HDL and can be implemented in FPGA. To our knowledge this is the first audio subword sorter unit implemented in FPGA

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Section: Enhanced Merge Sorter Network (Ems)mentioning

confidence: 99%

Section: Modified Enhanced Merge Sorter Network (Mems)mentioning

confidence: 99%

“…The paper [3] expounds only the sorting technique at the transmitter side. It does not give any method to retrieve (decrypt) the data at the receiving end.…”

Section: Modified Enhanced Merge Sorter Network (Mems)mentioning

confidence: 99%

“…New structure has been designed for both the left and right data path separately. The designed structures are simpler and more efficient than the ones existing [3].…”

Section: Modified Enhanced Merge Sorter Network (Mems)mentioning

confidence: 99%

Section: Levelmentioning

confidence: 99%

See 3 more Smart Citations

Hardware Implementation of Low Power Audio Sub word Sorter Unit for High SecurityTransmission

Karthigaikumar¹,

Baskaran²

2009

IJCEE

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Exploring the design space of programmable regular expression matching accelerators

Atasu

Polig

Rohrer

et al. 2013

Journal of Systems Architecture

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Hardware-accelerated regular expression matching for high-throughput text analytics

Atasu

Polig

Hagleitner

et al. 2013

2013 23rd International Conference on Field Programmable Logic and Applications

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Advanced text analytics systems combine regular expression (regex) matching, dictionary processing, and relational algebra for efficient information extraction from text documents. Such systems require support for advanced regex matching features, such as start offset reporting and capturing groups. However, existing regex matching architectures based on reconfigurable nondeterministic state machines and programmable deterministic state machines are not designed to support such features. We describe a novel architecture that supports such advanced features using a network of state machines. We also present a compiler that maps the regexs onto such networks that can be efficiently realized on reconfigurable logic. For each regex, our compiler produces a state machine description, statically computes the number of state machines needed, and produces an optimized interconnection network. Experiments on an Altera Stratix IV FPGA, using regexs from a real life text analytics benchmark, show that a throughput rate of 16 Gb/s can be reached.

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Sorter Based Permutation Units for Media-Enhanced Microprocessors

Cited by 10 publications

References 14 publications

Hardware Implementation of Low Power Audio Sub word Sorter Unit for High SecurityTransmission

Hardware Implementation of Low Power Audio Sub word Sorter Unit for High SecurityTransmission

Exploring the design space of programmable regular expression matching accelerators

Hardware-accelerated regular expression matching for high-throughput text analytics

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