Source/Drain Engineering for In_0.7Ga_0.3As N-Channel Metal–Oxide–Semiconductor Field-Effect Transistors: Raised Source/Drain with In situ Doping for Series Resistance Reduction

Abstract

In this paper, we report N-channel metal–oxide–semiconductor field-effect transistors (N-MOSFETs) featuring in situ doped raised In0.53Ga0.47As source/drain (S/D) regions. This is the first demonstration of such regrowth on an In0.7Ga0.3As channel. After SiON spacer formation, the raised In0.53Ga0.47As S/D structure was formed by selective epitaxy of In0.53Ga0.47As in the S/D regions by metal-organic chemical-vapor deposition (MOCVD). In situ silane SiH4 doping was also introduced to boost the N-type doping concentration in the S/D regions for series resistance R SD reduction. The raised S/D structure contributes to I Dsat enhancement for the In0.7Ga0.3As N-MOSFETs.

A Self-Aligned Ni-InGaAs Contact Technology for InGaAs Channel n-MOSFETs

“…[18][19][20][21][22][23][24][25][26][27][28][29] To realize the high performance of InGaAs channel MOSFETs, reliable and low-resistance ohmic contacts to In-GaAs also need to be developed. [30][31][32][33][34][35][36][37][38][39][40][41][42][43][44] In addition, self-alignment of the source/drain (S/D) contacts to the gate electrode is desirable for reduced S/D access resistances and for achieving reduced transistor footprint. Although a height-selective-etching process has been developed to achieve self-aligned contacts for III-V MOSFETs, 45,46 a self-aligned metallization process is still preferred.…”

RF reliability of gate last InGaAs nMOSFETs with high-k dielectric

“…The advantages of this structure are the preservation of the high mobility to the extrinsic device [2], low source/drain resistance due to high doping incorporation [5] and a good control of the high-k/InGaAs interface [2]. After deposition of a SiO 2 -like dummy gate, the Sn-doped 40-nm-thick raised source/drain is grown epitaxially on top of a not intentionally doped 10-nm-thick In 0.53 Ga 0.47 As channel.…”

“…Due to the high injection velocity and mobility, it is possible to reach high on-current at low source/drain voltages [2]. The high-k to channel interface quality and source/drain series resistance are challenges that have been addressed and improved by many different groups [2][3][4][5][6]. There are many studies on the relevant reliability issues of high-k/silicon transistors [7][8][9][10], but only few studies concerning high-k MOSFETs on InGaAs substrates [11][12].…”

N-Channel InGaAs Field-Effect Transistors formed on Germanium-on-Insulator Substrates

“…Figure 4 benchmarks the normalized peak transconductance G m of devices in this work with the state-of-the-art In x Ga 1Àx As transistors reported in the literature. [21][22][23][24][25][26][27][28][29][30] The peak G m was normalized with equivalent oxide thickness (t ox ) to account for the difference in high-k dielectric thickness in the various reports. Our data (black solid symbols) fits very well with other reported values on the inverse proportional trend of G m versus L G .…”