Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications

Mallikarjunarao,; Ranjan, Rajeev; Pradhan, K P; Artola, L.; Sahu, Prasanna Kumar

doi:10.1016/j.spmi.2016.06.010

Cited by 15 publications

(3 citation statements)

References 19 publications

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“…The usage of different dielectric materials and their impact was reported to be conducive to circumvent the problems in tunnel FETs. 20,21 High-K dielectric materials, when used in a gate oxide, offer high electrostatic integrity. This explicitly indicates a better gate control over the channel which does away with the malaise caused by the rudimentary limit on MOSFET's subthreshold slope.…”

Section: Resultsmentioning

confidence: 99%

Dielectric Pocket-Pocket Intrinsic Triple Gate TFET for Low Power Application: A Device Level Analysis

Bantupalli

Panchanathan

2021

ECS J. Solid State Sci. Technol.

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This report investigates a novel dielectric pocket-pocket intrinsic triple gate tunnel field effect transistor to magnify a device's performance well suited for low-power applications. The source engineering which was adopted here using DP and PI has resulted in improved drive current of the device. A heterojunction was also formed between low bandgap energy materials and silicon, at the source side, to escalate the carrier tunneling at the interface of source and channel. Gate-drain overlapping technique, usage of high bandgap materials in drain region along with high-K dielectric materials in oxides ensured low ambipolar current, low off current, and a steeper subthreshold slope respectively. With these traits, the proposed device is believed to be suitable for lowpower applications. The proposed structure is simulated, and the electrical parameters are analysed using the SILVACO TCAD ATLAS tool.

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Section: Resultsmentioning

confidence: 99%

Dielectric Pocket-Pocket Intrinsic Triple Gate TFET for Low Power Application: A Device Level Analysis

Bantupalli

Panchanathan

2021

ECS J. Solid State Sci. Technol.

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“…[8][9][10] In addition, it seems to be a problem that many ideas for TFET device structures are proposed to obtain better characteristics on the basis of device simulation without examining the drain-bias-dependent transfer curves precisely. [11][12][13][14][15][16] We have experimentally examined silicon-based TFETs 17,18) and found a definite drain bias dependence of transfer characteristics even in long-channel cases. This is an important aspect of TFETs to be understood from the standpoints of both device design and circuit design.…”

Section: Introductionmentioning

confidence: 98%

On the drain bias dependence of long-channel silicon-on-insulator-based tunnel field-effect transistors

Fukuda

Mori

Asai

et al. 2017

Jpn. J. Appl. Phys.

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The drain bias dependence of tunnel field-effect transistors (TFETs) is examined on the basis of the measured characteristics and device simulation to understand the electrical behavior of TFETs. Our analyses focus on the long-channel silicon-on-insulator (SOI)-based TFETs as a good basis for further studies of short-channel effects, scaling issues, and more complicated device structures, such as multigate or nanowire TFETs. By device simulation, it is revealed that the drain bias dependence of the transfer characteristics of the measured TFETs is governed by two physical mechanisms: the density of states (DOS) occupancy factor, which depends on drain-to-source bias voltage, and channel electrostatic potential, which is limited by the drain bias through strong carrier accumulation. These mechanisms differ from the drain-induced barrier lowering (DIBL) of metal–oxide–semiconductor field-effect-transistors (MOSFETs), and cause a significant impact even in long-channel SOIs. Finally, the obtained insights are successfully implemented in a TFET compact model.

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“…Since the power dissipation is proportional to the device operating voltage, a single effective way to reduce the power dissipation is to lower the subthreshold swing of the devices, which enables the using of a lower supply voltage. [1,2] However, due to the carrier injection mechanism, the subthreshold swing of traditional MOSFET is limited to 60 mV/dec at room temperature. [3,4] Hence, tunneling field-effect transistor (TFET) which is essentially a gated P-i-N diodehas been explored and attracted much interest in recent years.…”

Section: Introductionmentioning

confidence: 99%

Simulation study of device physics and design of GeOI TFET with PNN structure and buried layer for high performance*

Wang¹,

Hu(胡晟)²,

Feng³

et al. 2020

Chinese Phys. B

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Large threshold voltage and small on-state current are the main limitations of the normal tunneling field effect transistor (TFET). In this paper, a novel TFET with gate-controlled P+N+N+ structure based on partially depleted GeOI (PD-GeOI) substrate is proposed. With the buried P+-doped layer (BP layer) introduced under P+N+N+ structure, the proposed device behaves as a two-tunneling line device and can be shut off by the BP junction, resulting in a high on-state current and low threshold voltage. Simulation results show that the on-state current density I on of the proposed TFET can be as large as 3.4 × 10−4 A/μm, and the average subthreshold swing (SS) is 55 mV/decade. Moreover, both of I on and SS can be optimized by lengthening channel and buried P+ layer. The off-state current density of TTP TFET is 4.4 × 10−10 A/μm, and the threshold voltage is 0.13 V, showing better performance than normal germanium-based TFET. Furthermore, the physics and device design of this novel structure are explored in detail.

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Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications

Cited by 15 publications

References 19 publications

Dielectric Pocket-Pocket Intrinsic Triple Gate TFET for Low Power Application: A Device Level Analysis

Dielectric Pocket-Pocket Intrinsic Triple Gate TFET for Low Power Application: A Device Level Analysis

On the drain bias dependence of long-channel silicon-on-insulator-based tunnel field-effect transistors

Simulation study of device physics and design of GeOI TFET with PNN structure and buried layer for high performance*

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