Spatial and Temporal Data Path Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures

Abstract

In this contribution we apply a novel strategy for partial remapping to significantly enhance the reliability of coarse-grained reconfigurable architectures. If a component of the architecture is affected by a permanent error, it will be deactivated and the architecture is reconfigured to relinquish the concerned resource. This is achieved by spatially moving operations from defective to unused components. If no unused component is available, operations are additionally moved within time domain to free the required resources. In our experiments, we regard the failure of each single component in an array of processing elements. Depending on the resource usage of the application, between 70% and 100% of the defects can be tolerated. In average, the repair of one failure takes 36 seconds, and the clock frequency has to be reduced by just 0.8% to enable the execution of the changed application mapping.

Adaptive multi-layer techniques for increased system dependability

“…The first task in our remapping flow [21] is the Architecture Correction. The system keeps an internal representation of the architecture and in case of a failure this representation is corrected such that it represents the current state of the architecture.…”

“…This work is part of the DFG funded priority program SPP 1500 "Dependable Embedded Systems"¹. The paper covers three projects related to system-and hardwarearchitecture, namely VirTherm-3D (system-level task mapping and communication) [12][13][14], OTERA (FGRP) [15][16][17], and ARES (CGRA) [18][19][20][21]. It is part of the IT special issue on "Embedded Systems".…”

Increasing Reliability Using Adaptive Cross-Layer Techniques in DRPs: Just-Safe-Enough Responses to Reliability Threats

“…To reduce the work-load of the SoC's CPU, we proposed an incremental remapping algorithm in [13]. First, the architecture graph is adjusted by removing the faulty components.…”