Specification and design of embedded hardware-software systems

Gajski, Daniel D.; Vahid, Frank

doi:10.1109/54.350695

Cited by 174 publications

(107 citation statements)

References 31 publications

Supporting

Mentioning

105

Contrasting

Unclassified

Order By: Relevance

“…The results show t h a t the resultant designs using the 2-point and 3-point A T projection methods required 27,057 and 23,672 gates to achieve the same timing. Figures 4,5,6, and 7 show the comparisons between the nal designs generated using the actual and projected AT-curves of the SP, Elliptic Filter, controller, and SDRAM controller, respectively. The results show that in most cases the designs generated using the projected AT-curves are consistently re ected the designs generated using the actual AT-curves.…”

Section: Methodsmentioning

confidence: 99%

“…K u c uk cakar and Parker 5] proposed estimation techniques to perform designspace exploration and evaluation to support systemlevel partitioning. In addition, quality measures and estimation techniques for high-and system-level synthesis have been addressed in 3,6].…”

Section: Related Workmentioning

confidence: 99%

“…In high-level design, design tradeo s can be obtained by exploring design architectures, schedules, and modules 4,5,6]. In RTL design, design tradeo s can be obtained by exploring target libraries, optimization procedures and physical e ects.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An RTL design-space exploration method for high-level applications

Kao

Hsieh

2001

Proceedings of the 2001 Conference on Asia South Pacific Design Automation - ASP-DAC '01

View full text Add to dashboard Cite

In this paper, we present an RTL design-space exploration method for high-level applications. We formulate the RTL design-space exploration into a performance-driven module selection problem. We devise a dynamic-programming algorithm to solve the problem. We present an exploration ow by integrating commercial synthesis and layout tools with our proposed method. Experimental results have demonstrated that generating AT-curve for all modules is the most time consuming task in the design-space exploration process. Using the proposed 3 -p oint AT p r ojection approach, our method c an achieve on an average of 80% speed-up in run time and 90% accuracy in design estimation.

show abstract

Section: Methodsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

An RTL design-space exploration method for high-level applications

Kao

Hsieh

2001

Proceedings of the 2001 Conference on Asia South Pacific Design Automation - ASP-DAC '01

View full text Add to dashboard Cite

show abstract

“…Unlike SUIF and Spark, our re-coder specifically aims at re-coding a C reference implementation into models in SLDLs suitable for design space exploration and system synthesis. The SpecSyn [3] synthesis system expects input specification in the SpecCharts language, but provides no facilities to create the initial SpecChart model. Our transformations are interactive and give the designer complete control ("designer-in-the-loop") to code/re-code the C reference model in order to arrive at the most suitable design implementation.…”

Section: 21mentioning

confidence: 99%

An Interactive Model Re-Coder for Efficient SoC Specification

Chandraiah

Dömer

IFIP – The International Federation for Information Processing

View full text Add to dashboard Cite

To overcome the complexity in System-on-Chip (SoC) design, researchers have developed sophisticated design flows that significantly reduce the development time through automation. However, while much work has focused on synthesis and exploration tools, little has been done to support the designer in writing and rewriting SoC models. In fact, our studies on industrial size examples have shown that about 90% of the system design time is spent on coding and re-coding of SLDL models, even in the presence of algorithms given in the form of C code. Since the quality of the design model has tremendous impact on the cost and quality of the resulting system implementation, creating and optimizing the model is a critical task toward successful SoC design.In this paper, we present an interactive source re-coder which integrates static analysis and code transformation tools into an editor to assist the designer in tedious modeling and optimization tasks. This novel approach allows the designer to use her/his limited modeling time efficiently, and thus yields significant gains in productivity.Keywords: System-level Design, Specification Modeling, Embedded systems, System-on-Chip INTRODUCTIONIn the past, the system-level design community has focused on solving various problems of system synthesis. Researchers have been working towards design automation at various abstraction levels with the goal to automate steps in the design process and reduce the design time. Motivated by the need to meet the time to market and aggressive design goals like low power, high performance, and low cost, researchers have * This work was supported in part by Nicholas Endowment through the Henry T. Nicholas III Research Fellowship. Pramod Chandraiah and Rainer Dömerproposed various design methodologies for effective design development, including top-down and bottom-up approaches. All these technological advances have significantly reduced the development time of embedded systems. However, design time is still a bottleneck in the production of systems, and further reduction through automation is necessary. One critical aspect neglected in optimization efforts so far is the design specification phase, where the intended design is captured and modeled for use in the design flow. Each design methodology expects a specific type of input model and most methodologies depend on intermediate design models for interaction between tools and the designer. The specification needs to be either hand-written from scratch, or modified from a reference model. While much of the research has focused on SoC synthesis and refinement tools, little has been done to support the designer in forming these models. MotivationIn order to study the intricacies and complications involved in writing a system specification, we have applied a top-down design methodology, as shown in Figure 1, to the example of a multimedia application, a MP3 audio decoder. Here, the design process starts with an abstract specification model which is then refined to create models at lower a...

show abstract

“…In addition, the system assigns each task to a processing element and ensures that tasks which need to communicate with each other are capable of doing so. Finally, schedules are produced for tasks and communication, such that real-time constraints are met [5], [6]. Co-synthesis systems generate feasible, low-cost architectures without designer intervention.…”

Section: Introductionmentioning

confidence: 99%