SPICE modeling of nonlinear memristive behavior

Abstract

Summary The recent discovery of the ‘modern’ memristor has drawn great attention of both academia and industry. Given their favorable performance merits, memristors are expected to play a fundamental role in electronic industry. Modeling of memristive devices is essential for circuit design, and a number of Simulation Program with Integrated Circuit Emphasis (SPICE) models have already been introduced. The common problem in most models is that there is no threshold consideration; hence, only a few address the nonlinear nature of the device. This paper aims to present a SPICE implementation of a threshold‐type switching model of a voltage‐controlled memristive device that attributes the switching effect to a tunneling distance modulation. Threshold‐type switching is closer to the actual behavior of most experimentally realizable memristive systems, and our modeling approach addresses the issue of programming thresholds. Both the netlist and the simple schematic are provided, thus making it easy to comprehend and ready to be used. Compared with other modeling solutions, it involves significantly low‐complexity operation under an unlimited set of frequencies, and its simulation results are in good qualitative and quantitative agreement with the theoretical formulation. The proposed model is used to simulate an antiserial memristive switch, proving that it can be efficiently introduced in complex memristive circuits. Copyright © 2013 John Wiley & Sons, Ltd.

Crossbar-Based Memristive Logic-in-Memory Architecture

“…2). In the simulations, we employed a SPICE-compatible threshold-type model of a voltage-controlled bipolar memristor, which attributes the resistance-switching effect to the modulation of an effective tunneling distance [23]. Values of the parameters of the model were set as: {a, b, c, m, f 0 , L 0 } = {15000, 0, 0.1, 82, 310}, with R OFF = 200KΩ, and R ON = 2KΩ.…”

“…The basic concept is to take advantage of a dense crossbar array that is heterogeneous in terms of its cross-point resistive devices while also using a novel group-accessing scheme for the selection lines of the target ReRAM cross-points. Our study particularly focuses on the ReRAM organization, taking into consideration: i) device-level memristor properties, by incorporating a threshold-type SPICEcompatible switching model of bipolar voltage-controlled memristors [23], [24]; ii) circuit-level properties, by adopting a functionally complete memristor-based digital logic design methodology that allows for single-step multi-input parallel logic computations [20]; and iii) architecture-level details assuming state-of-the-art high-density and CMOS-compatible memristor-transistor crossbar geometry with a group-accessed vertical (which could be thought of as a nano-pillar vertical gate-all-around or VGAA) transistor as the cross-point selector underneath each memristive device [25]- [27]. In this way we achieve: i) memory and logic operations through gate-controlled resistance switching with no current sneak-paths [28]; ii) a much smaller cell footprint compared to that of traditionally planar transistors; and iii) lower operating power compared to that of a typical passive cross-point array.…”

Employing threshold‐based behavior and network dynamics for the creation of memristive logic circuits and architectures

“…Threshold-type switching is closer to the actual behaviour of most experimentally realizable memristive devices [17]. Throughout this work, all conducted simulations employ a threshold-based device model of a voltage-controlled memristor which attributes its behaviour to a tunnelling distance modulation [19]. Such model is based on the assumption that the resistance switching rate of a memristor is fast when the applied voltage is above a threshold (namely V SET or V RESET ) which is viewed as the minimum voltage required to induce a change to the memristance of the device; there is negligible change induced to the memristance if the magnitude of the applied voltage remains below these thresholds.…”

“…Regarding the memristor circuit schematic, for a FPM the top terminal is the one with the thin line, whereas for a RPM it is the one with the thick line. According to the used device model [19], we assume that the memristance of a FPM will decrease/increase when the latter is forward/reversely biased, whereas a RPM has the opposite response.…”

Saddle-Node Bifurcations in Classical and Memristive Circuits

“…The memristor is meant to be the fourth basic circuit element, in addition to resistors, capacitors and inductors, whose characteristics relate voltage and current, voltage and charge, and flux and current, respectively. Some recent references on this topic are [Adamatzky and Chua, 2014;Buscarino et al, 2012;Di Ventra et al, 2009;Itoh and Chua, 2008;Corinto, 2011;García-Redondo et al, 2014;Chua, 2011, 2014;Jansen et al, 2013;Kavehei et al, 2010;Messias et al, 2010;Muthuswamy and Chua, 2010;Di Ventra, 2011, 2012;Vourkas et al, 2015;Tetzlaff, 2014].…”