Spiking Neuron Hardware-Level Fault Modeling

Abstract

The deployment of Artificial Intelligence (AI) hardware accelerators in a variety of applications, including safetycritical ones, requires assessing their inherent reliability to hardware-level faults and developing cost-effective fault tolerance techniques. This entails performing large-scale fault simulation experiments. However, transistor-level fault simulation is prohibitive and fault simulation should be carried out at a higher abstraction level. In this work, we focus on spiking neural networks (SNNs), and we follow a bottom-up approach starting from transistor-level simulations for developing a neuron behavioral-level fault model that can be readily employed for performing behavioral-level fault simulation of deep SNNs.

Neural Coding in Spiking Neural Networks: A Comparative Study for Robust Neuromorphic Systems

“…( Lewyn et al, 2009 ; Vatajelu E.I. et al, 2019 ; El-Sayed et al, 2020 ). Vatajelu E. et al (2019) reported and analyzed different generic fault models that could exist in SNN hardware implementation.…”

“… Vatajelu E. et al (2019) reported and analyzed different generic fault models that could exist in SNN hardware implementation. We chose the synaptic SAF model in this study since it appears very often in hardware, especially in the promising and newly emerging analog devices, and it has a profound impact on hardware performance ( El-Sayed et al, 2020 ; Kwon et al, 2020 ; Zhang B. et al, 2020 ). A SAF device has its conductance state fixed at either a high or low conductance state.…”

Neuron Fault Tolerance in Spiking Neural Networks

“…This capability stems from massively parallel architectures and overprovisioning. However, recent fault injection experiments in AI hardware accelerators have shown that they can be highly vulnerable to hardware-level faults especially when those are happening after training [3]- [11]. These experiments demonstrate that equipping AI hardware accelerators with a preventative fault tolerance strategy is a crucial requirement for mitigating risks in AI systems.…”

“…Fault injection experiments showing the vulnerability of SNNs to hardware-level faults have been presented in [6], [7], [11]. A built-in self-test strategy is proposed for a biologicallyinspired spiking neuron in [7].…”

“…Fault injection is accelerated by modeling neuron faults at behavioral-level and by embedding the faulty SNN in a GPU. For the fault modeling part, we rely on the findings of a recent work that performed transistor-level fault simulation at the neuron-level and collected all types of neuron faulty behaviors [11]. Next, we leverage the findings from our fault injection experiments to develop a cost-effective fault tolerance strategy consisting in multiple layers of protection.…”