Spin-Transfer Torque Memories: Devices, Circuits, and Systems

Fong, Xuanyao; Kim, Yusung; Venkatesan, Rangharajan; Choday, Sri Harsha; Raghunathan, Anand; Roy, Kaushik

doi:10.1109/jproc.2016.2521712

Cited by 171 publications

(77 citation statements)

References 211 publications

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“…Opportunities: Spin-Transfer Torque technology shows good potential as a replacement for both SRAM and DRAM memories. It shows good integration capabilities and potentially reduced fabrication cost, high operation speed, potentially to the level of L1 cache, high endurance and non-volatility [38,120,121].…”

Section: Opportunities and Challengesmentioning

confidence: 99%

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Challenges and Solutions in Emerging Memory Testing

Vatajelu

Prinetto

Taouil

et al. 2019

IEEE Trans. Emerg. Topics Comput.

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International audienceThe research and prototyping of new memory technologies are getting a lot of attention in order to enable new (computer) architectures and provide new opportunities for today’s and future applications. Delivering high quality and reliability products was and will remain a crucial step in the introduction of new technologies. Therefore, appropriate fault modelling, test development and design for testability (DfT) is needed. This paper overviews and discusses the challenges and the emerging solutions in testing three classes of memories: 3D stacked memories, Resistive memories and Spin-Transfer-Torque Magnetic memories. Defects mechanisms, fault models, and emerging test solutions will be discussed

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Section: Opportunities and Challengesmentioning

confidence: 99%

“…The write asymmetry limits their power efficiency and operation speed, since the memory is as fast as its slowest operation [120]. The spontaneous magnetic reversal limits the data retention time, causes read destructive faults, and imprints a probabilistic behaviour to the write operation [121].…”

Section: Opportunities and Challengesmentioning

confidence: 99%

Challenges and Solutions in Emerging Memory Testing

Vatajelu

Prinetto

Taouil

et al. 2019

IEEE Trans. Emerg. Topics Comput.

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“…Spin-Transfer Torque (STT) based device has been rapidly evaluated as one of the most promising spintronics applications [25] with several advantages [26]. A typical STT device is realized by a stacked multi-layer sandwich structure that composed mainly of these layers: an oxide tunnel barrier (TB), a free magnetic layer (FL) and a pinned magnetic layer (PL) as shown in Fig.…”

Section: B Spin-transfer and Spin-orbit Torque Mechanismmentioning

confidence: 99%

Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation

Yang

Wang

Zhou

et al. 2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Circuit obfuscation is a frequently used approach to conceal logic functionalities in order to prevent reverse engineering attacks on fabricated chips. Efficient obfuscation implementations are expected with lower design complexity and overhead but higher attack difficulties. In this paper, an emerging obfuscation approach is proposed by leveraging spinorbit torque (SOT) devices based look-up-tables (LUTs) as reconfigurable logic to replace the carefully selected gates. It is essentially impossible to identify the obfuscated gate with SOTs inside according to the physical geometry characteristics because the configured functionalities are represented by magnetization states. Such an obfuscation approach makes the circuit security further improved with high exponential attack complexities. Experiments on MCNC and ISCAS 85/89 benchmark suits show that the proposed approach could reduce the area overheads due to obfuscation by 10% averagely.

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“…These faults can occur as a consequence of the stochastic nature of the write operation, which makes the magnetization reversal a probabilistic operation. A device fabricated, for instance, with a free layer larger than nominal design, will require larger current for a highly probable write operation [53]. This means that when writing to such a cell, with nominal bias, the probability of magnetization reversal will be low, causing the state of the cell at the completion of the write operation to be arbitrary.…”

Section: Uwmentioning

confidence: 99%

State of the art and challenges for test and reliability of emerging nonvolatile resistive memories

Vatajelu

Pouyan

Hamdioui

2017

Circuit Theory & Apps

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Summary The power and reliability issues of today's memories (static and dynamic RAMs) reduce the advances achieved by their implementation in scaled technology. There are several emergent memory technologies that address the technical constraints of today's memories, among which the most promising solutions are the resistance‐based memories, such as phase change memories, the redox‐based resistive memories, and the spin‐transfer torque magnetic memories. These technologies are facing various challenges that have to be addressed to render them efficient in today's applications. Until recently, research focus was on the design for performance and power efficiency, but lately, the test and reliability issues of these devices have become of major concern to the community. This paper presents an overview of the challenges and proposed test and reliability boost solutions developed to suit the needs of the emerging memories under analysis. It underlines (1) the unique faults that occur in the memory cell due to known issues in the emerging storage devices, (2) the dedicated solutions developed for efficient testing of the emerging memories under study, (3) the main reliability concerns related to the emerging storage devices, and (4) the design solutions targeted at mitigating these reliability issues. Copyright © 2017 John Wiley & Sons, Ltd.

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Spin-Transfer Torque Memories: Devices, Circuits, and Systems

Cited by 171 publications

References 211 publications

Challenges and Solutions in Emerging Memory Testing

Challenges and Solutions in Emerging Memory Testing

Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation

State of the art and challenges for test and reliability of emerging nonvolatile resistive memories

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