Split gate SOI trench LDMOS with low-resistance channel

YingWang,; Wang, Yifan; Liu, Yan-juan; Yang-Wang,

doi:10.1016/j.spmi.2017.01.001

Cited by 12 publications

(2 citation statements)

References 12 publications

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“…RESURF using field plate effect of floating gate structures and their experimental analysis is reported in [9,10]. Numerical studies of power devices using vertical trenches with floating polysilicon are presented in [11][12][13][14][15]. In split-gate devices, however, inefficient shielding under high field conditions can lead to carrier generation and subsequently high impact ionization near active gate edges, both of which are critical concerns that can compromise the long-term reliability of the device.…”

Section: Introductionmentioning

confidence: 99%

Drain-extended MOS design using High-k dielectric to control off-state BTBT with enhanced switching performance

2022

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This work explores the application of high-k dielectric to suppress off-state band-to-band tunnelling (BTBT) and enhance the switching performance of conventional Drain-extended NMOS (C_DeNMOS). C_DeNMOS switching performance is limited by extended gate over the drift region, while the high field effects near the gate edge are responsible for BTBT below the gate-to-drain overlap region. We investigate two improved configurations of DeNMOS 1) Planar and 2) Trench structures incorporating a floating plate (FP). In comparison to C_DeNMOS, it is demonstrated that employing high-k dielectric HfO2 with appropriately doped FP in the Planar and Trench structures can efficiently modulate the surface field while also reducing surface charge accumulation. As a result, BTBT is suppressed in Planar and Trench structures when HfO2 is used as dielectric, in addition to improvement in switching delay, reverse recovery behavior, and switching energy performance at higher operating frequencies.

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Section: Introductionmentioning

confidence: 99%

Drain-extended MOS design using High-k dielectric to control off-state BTBT with enhanced switching performance

2022

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“…At the same time, low losses are also one of the main development directions of power LDMOS. The static losses are only related to the R on,sp , and the switching losses are related to the Q GD [7,8]. At rst, the oxide trench is introduced into the drift region to improve the contradictory relationship between R on,sp and BV [9][10][11].…”

Section: Introductionmentioning

confidence: 99%

A Novel LDMOS with Ultralow Specific on-Resistance and Improved Switching Performance

Zeng

et al. 2021

Silicon

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A stepped split triple-gate SOI LDMOS with P/N strip (P/N SSTG SOI LDMOS) is proposed, which has ultralow speci c on-resistance (R on,sp ) and low switching losses. The proposed device has a triple-gate (TG) and stepped split gates (SSGs). P strip, N-drift and oxide trench are alternately arranged in the Z direction. Meanwhile, the SSGs are located in the oxide trench of the N-drift region and are distributed in steps. Firstly, the TG increases the channel width (W ch ) and has the effect of modulating current distribution, resulting in lower R on,sp and higher transconductance (g m ). Secondly, the SSGs serve as the eld plate to assist the depletion of the N-drift region, increasing the optimal doping concentration of the N-drift region (N d-opt ) and further reducing the R on,sp . Moreover, the SSGs also have the effect of modulating the electric eld distribution to maintain a high breakdown voltage (BV). Meanwhile, gatedrain charge (Q GD ) and switching losses are reduced on account of the introduction of the SSGs. Thirdly, in the off-state, the P strip and SSGs multidimensional assisted depletion of the N-drift region, which greatly increases the N d-opt . The highly doped N-drift region provides a low-resistance path for the current, which also further reduces R on,sp . Compared with triple-gate (TG) SOI LDMOS with almost equal breakdown voltage, the R on,sp and Q GD of P/N SSTG SOI LDMOS are reduced by 62% and 63%, respectively.LDMOS is reduced by 63%, and the switching losses are signi cantly reduced. So the proposed device achieves an excellent tradeoff between R on,sp and Q GD . Besides, the proposed device is generally applied to medium and low rated voltages, substantially reducing power losses.

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A Lateral Double-Diffusion Metal Oxide Semiconductor Device with a Gradient Charge Compensation Layer

Ding

Chen

et al. 2019

Journal of Elec Materi

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Split gate SOI trench LDMOS with low-resistance channel

Cited by 12 publications

References 12 publications

Drain-extended MOS design using High-k dielectric to control off-state BTBT with enhanced switching performance

Drain-extended MOS design using High-k dielectric to control off-state BTBT with enhanced switching performance

A Novel LDMOS with Ultralow Specific on-Resistance and Improved Switching Performance

A Lateral Double-Diffusion Metal Oxide Semiconductor Device with a Gradient Charge Compensation Layer

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