Squeezing the chip: The buildup of compressive stress in a microprocessor chip by packaging and heat sink clamping

Measurement of die stresses in microprocessor packaging due to thermal and power cycling

“…For each sensor site, average values from the 40 tested packages were obtained. The details of these measurements were discussed in our earlier publication [16]. Analogous to many other packaging architectures, the maximum normal stresses (compressive) were found to be located at the center of the die, while the maximum shear stresses were found in the corners.…”

“…A sequential modeling approach was previously utilized by the authors to predict the build-up of die stress from the bare die configuration to a completely assembled ceramic LGA [16]. In the packaging process, chips are reflowed to the ceramic substrates, and then subsequently underfilled and cured.…”

“…Such results were also observed at other rosette sites. As a general "rule of thumb," approximately 2/3rds (~66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment (solder reflow) assembly step, and the smallest contribution coming from lid attachment [16].…”

“…In most applications, this pressure is typically obtained by the clamping forces exerted by a heat sink and bolster plate combination. In our work, it was essential that no additional stresses were added through the actual testing process and several clamps were developed for different stages of assembly [16].…”

“…We have also recently studied the build up in stress during the assembly of the flip chip ceramic ball grid array (FC-CBGA) configuration shown in Figure 1 [16]. Before packaging, the sensor resistances were measured by directly probing the test chip wafers.…”