SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect

Flexible cache error protection using an ECC FIFO

“…The combination of growing LLC capacity, shrinking SRAM cell dimensions, and increasing fabrication variability that reduces error margins is leading to a higher soft error rate (SER) [19,27,29]. In particular, recent trends show that multi-bit burst errors in the array are becoming significant, partially because many memory cells can fall under the footprint of a single energetic particle strike [19,21,26].…”

“…Researchers have already observed up to 16-bit errors in SRAM arrays and are predicting potentially higher counts in the future [1,19,21]. The more powerful error protection mechanisms required to correct large numbers of bit flips come at a cost of storing more redundant information or modifying physical designs, as well as increased energy requirements [12,23].…”

Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

“…In today's technologies, the majority of soft error events result in only a single cell being disturbed. However, as we scale into the nanometer regime, the single-event multi-bit upset rate exponentially increases because more memory cells fall under the footprint of a single energetic particle strike [29,34,41]. The extent of a single-event multi-bit error can range from disrupting a few bits to hundreds of bit flips along entire columns and rows [15,43].…”

“…The extent of a single-event multi-bit error can range from disrupting a few bits to hundreds of bit flips along entire columns and rows [15,43]. SRAM designs have already exhibited up to 16 bit corruptions in one dimension [5,29,34].…”

An Autonomous SRAM With On-Chip Sensors in an 80-nm Double Stacked Cell Technology

“…Density limitation due to relatively large cell size, increased leakage current arising from higher density, static noise margin of cell, and soft error rate from small cell node capacitance are major concerns for SRAM engineers [1], [2].…”