SRAM With Stability Monitoring and Body Bias Tuning for Biomedical Applications

Abstract

This work presents a novel low leakage SRAM architecture with always-retention and local wake-up. To tackle the large design margins in deep sub-micron technology nodes, it includes SNM monitoring and compensation circuitry to track variation across the memory array. This allows for operation close to the point of first failure. As proof of concept, a macro of 1Mbit is fabricated in 22nm FDSOI. Measurements show an active energy of 3.6 pJ/access at 6.6 MHz and a leakage power of 0.19 pW/cell, a reduction of 53.8% due to margin reduction.

A 1MHz 256kb Ultra Low Power Memory Macro for Biomedical Recording Applications in 22nm FD-SOI Using FECC to Enable Data Retention Down to 170mV Supply Voltage

“…Additionally, these works still require margins for global and local variation. Alternatively, when an SOI technology is used, body biasing can be used to tune individual dies to remove the margin of global variation [1], [8], [13] or even within a die, to even remove some systematic local variation margins [22]. This tuning is either done during start-up, using a BIST to check all the cells using predefined memtest patterns [1], [7], [8], [12], [13] or it uses the replica monitor cell technique [17], [22] from the second category.…”

“…Alternatively, when an SOI technology is used, body biasing can be used to tune individual dies to remove the margin of global variation [1], [8], [13] or even within a die, to even remove some systematic local variation margins [22]. This tuning is either done during start-up, using a BIST to check all the cells using predefined memtest patterns [1], [7], [8], [12], [13] or it uses the replica monitor cell technique [17], [22] from the second category. However, these techniques still require some margin to guarantee functionality during long operation of the macro, to mitigate local variation, drift and ageing effects.…”

“…Additionally, adding multiple spare words increases the complexity of the wordline decoder significantly. When a memory macro is subdivided in local blocks (LB), one could use this already present granularity to enable FECC on LB level, similar to the idea of using the LB level for bulk bias trimming [22]. Now, the FECC is used as an in-situ monitor instead of the replica monitor in [22].…”

“…When a memory macro is subdivided in local blocks (LB), one could use this already present granularity to enable FECC on LB level, similar to the idea of using the LB level for bulk bias trimming [22]. Now, the FECC is used as an in-situ monitor instead of the replica monitor in [22]. A trade-off can be made: a more aggressive voltage scaling for lower leakage results in more errors, which require more LBs to be in an ECC mode, which increases dynamic power.…”

“…However, the area overhead for this technique is significant. A more intermediate granularity can be used on LB level [22]. This work uses this intermediate granularity and switches LBs.…”