Stability improvement of amorphous InGaZnO TFTs by an asymmetric design

Abstract

In this reported work, amorphous InGaZnO thin film transistors (TFTs) with symmetric and asymmetric structures are fabricated. A constant positive gate bias for a time of 1-5 × 10 4 s was then applied to the TFTs to investigate their performance variation. The mobilities of the TFTs were not significantly degraded by a long stress time of 5 × 10 4 s. Also, decreases of sub-threshold swing and off-state current were observed for a stress time of 10 4 s. Although significant threshold voltage variation was found for the a-IGZO TFT with a symmetric design during the stress test, it could be reduced by 56% for the TFT fabricated by the proposed asymmetric design.

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