STABLE: Stress-Aware Boolean Matching to Mitigate BTI-Induced SNM Reduction in SRAM-Based FPGAs

Ghaderi, Zana; Bagherzadeh, Nader; Albaqsami, Ahmad

doi:10.1109/tc.2017.2725952

Cited by 10 publications

(3 citation statements)

References 34 publications

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“…With the development of processor architecture, high-performance heterogeneous multicore processors are emerging. Because the design of a highperformance heterogeneous multicore processor is very complex, in order to reduce the design risk, shorten the mapping cycle, carry out software development ahead of time, and reproduce the problems after silicon, it usually needs the prototype mapping architecture of FPGA (fieldprogrammable gate array) and carries out a variety of hardware and software collaborative mapping and debugging works based on FPGA architecture [10]. e proposed FPGA debugging and mapping method for heterogeneous multicore high-performance processors based on isomorphic FPGA architecture effectively utilizes the architecture characteristics of heterogeneous multicore processors and the symmetry characteristics of isomorphic FPGA, divides FPGA from top to bottom in a hierarchical way, and constructs FPGA architecture from bottom to top [11].…”

Section: Fpga Architecture and Process Mapping Algorithmmentioning

confidence: 99%

FPGA Delay-Oriented Process Mapping Algorithm of Xiangxi Minority Based on LUT

Yun

Zeng

Zhang

2022

Mathematical Problems in Engineering

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At present, FPGA (field-programmable gate array) architecture has made great progress in the requirements of hardware volume, which can meet common needs. However, for the increasing number of resources, it is difficult to significantly reduce the delay of process mapping. Therefore, this paper proposes FDMAP (fit descending map) algorithm from the perspective of the LUT number to reduce the delay. This paper proposes a method of FPGA mapping and debugging for heterogeneous multicore high-performance processors based on isomorphic symmetric FPGA architecture, which effectively utilizes the architectural features of heterogeneous multicore processors and the symmetric features of isomorphic FPGA, divides FPGA functions from top to bottom in a hierarchical way, and constructs FPGA architecture from bottom to top. Using differential bridge and adaptive delay adjustment sampling technology, combined with the embedded virtual logic analyzer debugging tool, FPGA architecture can be lightened and deployed quickly. Multicore complementary core-to-core replacement simulation mapping methods such as debug shells can be used to effectively complete the mapping of the target’s high-performance heterogeneous multicore processor to the entire SOC (system on-ship) chip system-level FPGA. In the aspect of algorithm, the fdmap algorithm is mainly implemented, and the low latency mapping of resources is realized with FPGA architecture. In order to verify the effectiveness of mapping the fdmap algorithm, this paper compares the fdmap algorithm with the vector VM algorithm. The research shows that when the wavelength resolution is 7 pm and the temperature error is less than 1°C, the shell is debugged, and 10 mapping examples are simulated with the fdmap algorithm. In the experiment, the LUT with the most critical 20% is selected, and the closed value of the LUT search type is set to 0.86. Compared with the original data, the number of LUTs increased by 15.2%, and the criticality decreased by 35.21%. Compared with the vector VM algorithm with the biggest gap, the number of LUTs decreased by 14.25%, the criticality improved by 14.21%, and the overall delay decreased by 65%. Therefore, the isomorphic symmetric FPGA architecture proposed in this paper can improve the structural criticality and significantly reduce the latency while reducing the number of LUTs.

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Section: Fpga Architecture and Process Mapping Algorithmmentioning

confidence: 99%

FPGA Delay-Oriented Process Mapping Algorithm of Xiangxi Minority Based on LUT

Yun

Zeng

Zhang

2022

Mathematical Problems in Engineering

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“…Since a SAT solver can help solve the problem of NPN Boolean matching and because many quick SAT solvers can be utilized, many Boolean matching algorithms based on SAT have emerged in recent years. The authors of [16][17][18][19][20] studied SAT-based Boolean matching. Based on graphs, simulation and SAT, Matsunaga [16] achieved PP-equivalence Boolean matching with larger inputs and outputs.…”

Section: Related Workmentioning

confidence: 99%

“…Based on graphs, simulation and SAT, Matsunaga [16] achieved PP-equivalence Boolean matching with larger inputs and outputs. The authors of [17,18] studied Boolean matching for FPGAs utilizing SAT technology.…”

Section: Related Workmentioning

confidence: 99%

A New Pairwise NPN Boolean Matching Algorithm Based on Structural Difference Signature

et al. 2018

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In this paper, we address an NPN Boolean matching algorithm. The proposed structural difference signature (SDS) of a Boolean function significantly reduces the search space in the Boolean matching process. The paper analyses the size of the search space from three perspectives: the total number of possible transformations, the number of candidate transformations and the number of decompositions. We test the search space and run time on a large number of randomly generated circuits and Microelectronics Center of North Carolina (MCNC) benchmark circuits with 7–22 inputs. The experimental results show that the search space of Boolean matching is greatly reduced and the matching speed is obviously accelerated.

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BAS: A BTI-based aging aware synthesis in FPGAs

Abednazari

Beitollahi

2022

Microelectronics Reliability

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STABLE: Stress-Aware Boolean Matching to Mitigate BTI-Induced SNM Reduction in SRAM-Based FPGAs

Cited by 10 publications

References 34 publications

FPGA Delay-Oriented Process Mapping Algorithm of Xiangxi Minority Based on LUT

FPGA Delay-Oriented Process Mapping Algorithm of Xiangxi Minority Based on LUT

A New Pairwise NPN Boolean Matching Algorithm Based on Structural Difference Signature

BAS: A BTI-based aging aware synthesis in FPGAs

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