Stacked PMOS clamps for high voltage power supply protection

Maloney, Timothy J.; Kan, W.

doi:10.1109/eosesd.1999.818992

Cited by 31 publications

(5 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The total gate current of Mc1 is equal to the total gate current through the oxide of Mn, which can be derived as (4) The voltage differences between the source and drain of both Mc1 and Mn are 0 V, so that the gate-to-drain current and the gate-to-source current should be the same. Therefore, (4) can be simplified to the component of only gate-to-source current for Mc1 and Mn, which can be derived as (5) The total gate-to-source current of Mc1 in the (5) can be solved by the given voltage of 0.3 V with the device parameters provided from foundry, which can be roughly calculated as (6) With consideration of the RC time constant, the W/L of MOS capacitor Mc1 is chosen as 5 m/5 m, and the total gate-tosource current of Mc1 can be determined by (6). Therefore, the device dimension of Mn can also be determined by (5).…”

Section: New Proposed Ultra-low-leakage Power-rail Esd Clamp Cirmentioning

confidence: 99%

“…Such a leaky ESD protection circuit is barely tolerable in portable products with low power requirements. High-voltage-tolerant power-rail ESD clamp circuits with only thin-oxide devices have been reported to overcome the gate-oxide reliability issue [6]- [8]. However, the prior designs did not consider the effect of gate leakage current if such circuits are further implemented in nanometer CMOS processes.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology

Wang

Ker

2009

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

An ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current. By controlling the gate current of the devices in the ESD detection circuit under a specified bias condition, the whole power-rail ESD clamp circuit can achieve an ultra-low standby leakage current. The new proposed circuit has been fabricated in a 1 V 65 nm CMOS process for experimental verification. The new proposed power-rail ESD clamp circuit can achieve 7 kV HBM and 325 V MM ESD levels while consuming only a standby leakage current of 96 nA at 1 V bias in room temperature and occupying an active area of only 49 m 21 m. Index Terms-Electrostatic discharge (ESD), gate leakage, power-rail ESD clamp circuit, silicon controlled rectifier (SCR).

show abstract

Section: New Proposed Ultra-low-leakage Power-rail Esd Clamp Cirmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology

Wang

Ker

2009

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

show abstract

“…In the mixed-voltage circuit application, the stacked nMOS structure had been widely used in the mixed-voltage input/output (I/O) buffer [15] to solve the gate-oxide reliability issue without using the additional thick-gate-oxide process (also known as dual gate oxide in some CMOS processes) [16], or the power-rail ESD clamp circuit [17]. Unfortunately, in such mixed-voltage I/O circuits, the stacked nMOS often have a much lower ESD level, as compared to the buffer with single nMOS [18], [19].…”

Section: Introductionmentioning

confidence: 99%

ESD implantation for subquarter-micron cmos technology to enhance ESD robustness

Ker

Hsu

Peng

2003

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

A new electrostatic discharge (ESD) implantation method is proposed to significantly improve ESD robustness of CMOS integrated circuits in subquarter-micron CMOS processes, especially the machine-model (MM) ESD robustness. By using this method, the ESD current is discharged far away from the surface channel of nMOS, therefore the nMOS (both single nMOS and stacked nMOS) can sustain a much higher ESD level. The MM ESD robustness of the gate-grounded nMOS with a device dimension width/length (W/L) of 300 m/0.5 m has been successfully improved from the original 450 V to become 675 V in a 0.25m CMOS process. The MM ESD robustness of the stacked nMOS in the mixed-voltage I/O circuits with a device dimension W/L of 300 m/0.5 m for each nMOS has been successfully improved from the original 350 V to become 500 V in the same CMOS process. Moreover, this new ESD implantation method with the n-type impurity can be fully merged into the general subquarter-micron CMOS processes.

show abstract

“…To solve the gate-oxide reliability issue without using the additional thick gate oxide process (also known as dual gate oxides in some CMOS processes [5], [6]), the stacked-MOS configuration has been widely used in the mixed-voltage I/O buffers [7]- [12], and in the power-rail ESD clamp circuits [13]. The typical 3-V/5-V-tolerant mixed-voltage I/O circuit is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%